MAIN MEMORY SYSTEM Mahdi Nazm Bojnordi Assistant Professor School - - PowerPoint PPT Presentation

MAIN MEMORY SYSTEM

CS/ECE 6810: Computer Architecture

Mahdi Nazm Bojnordi

Assistant Professor School of Computing University of Utah

Overview

¨ Announcement

¤ Tonight: Homework 4 submission deadline

¨ This and the following lectures

¤ Dynamic random access memory (DRAM) ¤ DRAM operations ¤ Memory scheduling basics ¤ Emerging memory technologies

Recall: DRAM Row Buffer

¨ All reads and writes are performed through RB

Data Array Row Buffer (RB) DRAM Cell DRAM Sense Amp. Row Access Strobe (RAS) Column Access Strobe (CAS)

DRAM Row Access

¨ DRAM read is destructive

¤ After a read, contents of cells are destroyed

Precharge Activate Sense Reading a zero Reading a one

DRAM Row Access

¨ DRAM read is destructive

¤ After a read, contents of cells are destroyed

Precharge Activate Sense Reading a zero Reading a one

V/2 ?

DRAM Row Access

¨ DRAM read is destructive

¤ After a read, contents of cells are destroyed

Precharge Activate Sense Reading a zero Reading a one

V/2 ? 1 V/2 ?

DRAM Row Access

¨ DRAM read is destructive

¤ After a read, contents of cells are destroyed

Precharge Activate Sense Reading a zero Reading a one

V/2 ? 1 V/2 ? 1 V/2 +

DRAM Row Access

¨ DRAM read is destructive

¤ After a read, contents of cells are destroyed

Precharge Activate Sense Reading a zero Reading a one

V/2 ? 1 V/2 ? 1 V/2 + V/2 ?

DRAM Row Access

¨ DRAM read is destructive

¤ After a read, contents of cells are destroyed

Precharge Activate Sense Reading a zero Reading a one

V/2 ? 1 V/2 ? 1 V/2 + V/2 ? 1 V/2 ?

DRAM Row Access

¨ DRAM read is destructive

¤ After a read, contents of cells are destroyed

Precharge Activate Sense Reading a zero Reading a one

V/2 ? 1 V/2 ? 1 V/2 + V/2 ? 1 V/2 ? 1 V/2 - V

DRAM Operations

¨ Main DRAM operations are

¤ Precharge bitlines to prepare subarray for activating a

wordline

¤ Activate a row by connecting DRAM cells to the bitlines

and start sensing

¤ Read the contents of a data block from the row buffer ¤ Write new contents for data block into the row buffer ¤ Refresh DRAM cells

n can be done through a precharge followed by an activate

DRAM Row Buffer

¨ Row buffer holds a single row of the array

¤ A typical DRAM row (page) size is 8KB

¨ The entire row is moved to row buffer; but only a

block is accessed each time

¨ Row buffer access possibilities

¤ Row buffer hit: no need for a precharge or activate

n ~20ns only for moving data between pins and RB

¤ Row buffer miss: activate (and precharge) are needed

n ~40ns for an empty row n ~60ns for on a row conflict

DRAM System

¨ DRAM chips can perform basic operations

CPU Chip Memory Modules DRAM Chips

DRAM Control

¨ DRAM chips have no intelligence

¤ An external controller dictates operations ¤ Modern controllers are integrated on CPU

¨ Basic DRAM timings are

¤ tCAS: column access strobe (RDàDATA) ¤ tRAS: row active strobe (ACTàPRE) ¤ tRP: row precharge (PREàACT) ¤ tRC: row cycle (ACTàPREàACT) ¤ tRCD: row to column delay (ACTàRD/WT) Data Array Row Buffer Decoder

DRAM Control

¨ DRAM chips have no intelligence

¤ An external controller dictates operations ¤ Modern controllers are integrated on CPU

¨ Basic DRAM timings are

¤ tCAS: column access strobe (RDàDATA) ¤ tRAS: row active strobe (ACTàPRE) ¤ tRP: row precharge (PREàACT) ¤ tRC: row cycle (ACTàPREàACT) ¤ tRCD: row to column delay (ACTàRD/WT) Data Array Row Buffer Decoder CPU DRAM Controller

Enforcing Timing

DRAM Timing Example

¨ Access time

¤ Row hit: tCAS ¤ Row empty: tRCD + tCAS ¤ Row conflict: tRP + tRCD + tCAS Data Array Row Buffer RD B RD A

X Y Requests

Cmd Addr Data

A B

DRAM Timing Example

¨ Access time

¤ Row hit: tCAS ¤ Row empty: tRCD + tCAS ¤ Row conflict: tRP + tRCD + tCAS Data Array Row Buffer RD B RD A

X Y Requests

Cmd Addr Data

A B Act X

DRAM Timing Example

¨ Access time

¤ Row hit: tCAS ¤ Row empty: tRCD + tCAS ¤ Row conflict: tRP + tRCD + tCAS Data Array Row Buffer RD B RD A

X Y Requests

Cmd Addr Data

A B Act X tRCD A

DRAM Timing Example

¨ Access time

¤ Row hit: tCAS ¤ Row empty: tRCD + tCAS ¤ Row conflict: tRP + tRCD + tCAS Data Array Row Buffer RD B RD A

X Y Requests

Cmd Addr Data

A B Act X A Rd tRCD A

DRAM Timing Example

¨ Access time

¤ Row hit: tCAS ¤ Row empty: tRCD + tCAS ¤ Row conflict: tRP + tRCD + tCAS Data Array Row Buffer RD B RD A

X Y Requests

Cmd Addr Data

A B Act X Data tCAS A Rd tRCD A

DRAM Timing Example

¨ Access time

¤ Row hit: tCAS ¤ Row empty: tRCD + tCAS ¤ Row conflict: tRP + tRCD + tCAS Data Array Row Buffer RD B

X Y Requests

Cmd Addr Data

A B Act X Data tCAS A Rd tRCD A

DRAM Timing Example

¨ Access time

¤ Row hit: tCAS ¤ Row empty: tRCD + tCAS ¤ Row conflict: tRP + tRCD + tCAS Data Array Row Buffer RD B

X Y Requests

Cmd Addr Data

A B Act X Data tCAS A Rd tRCD Pr tRAS A

DRAM Timing Example

¨ Access time

¤ Row hit: tCAS ¤ Row empty: tRCD + tCAS ¤ Row conflict: tRP + tRCD + tCAS Data Array Row Buffer RD B

X Y Requests

Cmd Addr Data

A B Act X Data tCAS tRP A Rd tRCD Pr tRAS

DRAM Timing Example

¨ Access time

¤ Row hit: tCAS ¤ Row empty: tRCD + tCAS ¤ Row conflict: tRP + tRCD + tCAS Data Array Row Buffer RD B

X Y Requests

Cmd Addr Data

A B Act X Data tCAS Act Y tRP A Rd tRCD Pr tRAS

DRAM Timing Example

¨ Access time

¤ Row hit: tCAS ¤ Row empty: tRCD + tCAS ¤ Row conflict: tRP + tRCD + tCAS Data Array Row Buffer RD B

X Y Requests

Cmd Addr Data

A B Act X Data tCAS Act Y tRP tRC A Rd tRCD Pr tRAS

DRAM Timing Example

¨ Access time

¤ Row hit: tCAS ¤ Row empty: tRCD + tCAS ¤ Row conflict: tRP + tRCD + tCAS Data Array Row Buffer RD B

X Y Requests

Cmd Addr Data

A B Rd B Act X Data tCAS Act Y tRP tRC A Rd tRCD Pr tRAS B

DRAM Timing Example

¨ Access time

¤ Row hit: tCAS ¤ Row empty: tRCD + tCAS ¤ Row conflict: tRP + tRCD + tCAS Data Array Row Buffer

X Y Requests

Cmd Addr Data

A B Rd B Data Act X Data tCAS Act Y tRP tRC A Rd tRCD Pr tRAS B