MAIN MEMORY SYSTEM Mahdi Nazm Bojnordi Assistant Professor School - PowerPoint PPT Presentation

MAIN MEMORY SYSTEM Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 6810: Computer Architecture

Overview ¨ Announcement ¤ Tonight: Homework 4 submission deadline ¨ This and the following lectures ¤ Dynamic random access memory (DRAM) ¤ DRAM operations ¤ Memory scheduling basics ¤ Emerging memory technologies

Recall: DRAM Row Buffer ¨ All reads and writes are performed through RB DRAM Cell Row Access Data Array Strobe (RAS) Column Access Row Buffer (RB) Strobe DRAM (CAS) Sense Amp.

DRAM Row Access ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense Reading a zero Reading a one

DRAM Row Access ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 0 Reading a zero ? Reading a one

DRAM Row Access ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 V/2 0 1 Reading a zero ? ? Reading a one

DRAM Row Access ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 V/2 V/2 + � 0 1 1 Reading a zero ? ? 0 Reading a one

DRAM Row Access ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 V/2 V/2 + � 0 1 1 Reading a zero ? ? 0 V/2 0 Reading a one ?

DRAM Row Access ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 V/2 V/2 + � 0 1 1 Reading a zero ? ? 0 V/2 V/2 0 1 Reading a one ? ?

DRAM Row Access ¨ DRAM read is destructive ¤ After a read, contents of cells are destroyed Precharge Activate Sense V/2 V/2 V/2 + � 0 1 1 Reading a zero ? ? 0 V/2 V/2 V/2 - � 1 0 1 Reading a one V ? ?

DRAM Operations ¨ Main DRAM operations are ¤ Precharge bitlines to prepare subarray for activating a wordline ¤ Activate a row by connecting DRAM cells to the bitlines and start sensing ¤ Read the contents of a data block from the row buffer ¤ Write new contents for data block into the row buffer ¤ Refresh DRAM cells n can be done through a precharge followed by an activate

DRAM Row Buffer ¨ Row buffer holds a single row of the array ¤ A typical DRAM row (page) size is 8KB ¨ The entire row is moved to row buffer; but only a block is accessed each time ¨ Row buffer access possibilities ¤ Row buffer hit: no need for a precharge or activate n ~20ns only for moving data between pins and RB ¤ Row buffer miss: activate (and precharge) are needed n ~40ns for an empty row n ~60ns for on a row conflict

DRAM System ¨ DRAM chips can perform basic operations CPU Chip DRAM Chips Memory Modules

DRAM Control ¨ DRAM chips have no intelligence ¤ An external controller dictates operations ¤ Modern controllers are integrated on CPU ¨ Basic DRAM timings are ¤ t CAS : column access strobe (RD à DATA) ¤ t RAS : row active strobe (ACT à PRE) ¤ t RP : row precharge (PRE à ACT) Row Buffer ¤ t RC : row cycle (ACT à PRE à ACT) Decoder ¤ t RCD : row to column delay (ACT à RD/WT) Data Array

DRAM Control ¨ DRAM chips have no intelligence ¤ An external controller dictates operations ¤ Modern controllers are integrated on CPU ¨ Basic DRAM timings are CPU ¤ t CAS : column access strobe (RD à DATA) DRAM Controller ¤ t RAS : row active strobe (ACT à PRE) ¤ t RP : row precharge (PRE à ACT) Row Buffer ¤ t RC : row cycle (ACT à PRE à ACT) Decoder ¤ t RCD : row to column delay (ACT à RD/WT) Data Array

Enforcing Timing

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS RD A ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS Row Buffer X A Data Array Y B Cmd Addr Data

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS RD A ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS Row Buffer X A Data Array Y B Cmd Act X Addr Data

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS RD A ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS A Row Buffer X A Data Array Y B t RCD Cmd Act X Addr Data

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS RD A ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS A Row Buffer X A Data Array Y B t RCD Cmd Act Rd X A Addr Data

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS RD A ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS A Row Buffer X A Data Array Y B t RCD Cmd Act Rd X A Addr Data Data t CAS

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS A Row Buffer X A Data Array Y B t RCD Cmd Act Rd X A Addr Data Data t CAS

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS A Row Buffer X A Data Array Y B t RAS t RCD Cmd Act Rd Pr X A Addr Data Data t CAS

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS Row Buffer X A Data Array Y B t RAS t RP t RCD Cmd Act Rd Pr X A Addr Data Data t CAS

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS Row Buffer X A Data Array Y B t RAS t RP t RCD Cmd Act Rd Pr Act X A Y Addr Data Data t CAS

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS Row Buffer X A Data Array t RC Y B t RAS t RP t RCD Cmd Act Rd Pr Act X A Y Addr Data Data t CAS

DRAM Timing Example ¨ Access time Requests RD B ¤ Row hit: t CAS ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS Row Buffer B X A Data Array t RC Y B t RAS t RP t RCD Cmd Act Rd Pr Act Rd X A Y B Addr Data Data t CAS

DRAM Timing Example ¨ Access time Requests ¤ Row hit: t CAS ¤ Row empty: t RCD + t CAS ¤ Row conflict: t RP + t RCD + t CAS Row Buffer B X A Data Array t RC Y B t RAS t RP t RCD Cmd Act Rd Pr Act Rd X A Y B Addr Data Data Data t CAS