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Lecture 12: Sequential Networks: Timing (contd), Standard Modules CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1 Clock Skew The

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SLIDE 1

Lecture 12: Sequential Networks: Timing (contd), Standard Modules

CSE 140: Components and Design Techniques for Digital Systems

Diba Mirza

  • Dept. of Computer Science and Engineering

University of California, San Diego

1

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SLIDE 2

Clock Skew

  • The clock doesn’t arrive at all registers at the same time
  • Skew is the difference between two clock edges
  • Examine the worst case to guarantee that the dynamic discipline is not

violated for any register – many registers in a system!

2

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SLIDE 3

Setup time constraint

3

Consider a circuit where the setup constraint is satisfied for R2 when there is no clock skew.

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SLIDE 4

Setup time constraint

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Is the setup constraint guaranteed to be satisfied if the rising edge of CLK2 arrives later than that of CLK1, i.e. CLK 2 is delayed (as shown in the figure ?

  • A. Yes
  • B. No

Consider a circuit where the setup constraint is satisfied for R2 when there is no clock skew.

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SLIDE 5

Setup Time Constraint with Clock Skew

  • In the worst case, the CLK2 is earlier than CLK1

Tc ≥ tpcq + tpd + tsetup + tskew tpd ≤ Tc – (tpcq + tsetup + tskew)

CLK1 Q1 D2 Tc tpcq tpd tsetuptskew C L CLK2 CLK1 R1 R2 Q1 D2 CLK2

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SLIDE 6

Timing Analysis with clock skew

CLK CLK A B C D X' Y' X Y

Timing Characteristics

tccq = 30 ps tpcq = 50 ps tsetup = 60 ps thold = 70 ps tpd = 35 ps tcd = 25 ps tskew = 50 ps

tpd = 3 x 35 ps = 105 ps tcd = 25 ps Setup time constraint: What is the minimum allowable clock period given that the clocks are skewed by 50ps?

  • A. 215ps
  • B. 265 ps
  • C. None of the above

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SLIDE 7

Timing Analysis with clock skew

CLK CLK A B C D X' Y' X Y

Timing Characteristics

tccq = 30 ps tpcq = 50 ps tsetup = 60 ps thold = 70 ps tpd = 35 ps tcd = 25 ps tskew = 50 ps

tpd = 3 x 35 ps = 105 ps tcd = 25 ps Setup time constraint: Tc ≥ 265 ps fc = 1/Tc =3.77 GHz Without skew we got fc =4.65 GHz

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SLIDE 8

Hold Time Constraint with Clock Skew

  • In the worst case, CLK2 is later than CLK1

tccq + tcd > thold + tskew tcd > thold + tskew – tccq

tccq tcd thold Q1 D2 tskew C L CLK2 CLK1 R1 R2 Q1 D2 CLK2 CLK1

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SLIDE 9

Hold Time Violation

Timing Characteristics

tccq = 30 ps tpcq = 50 ps tsetup = 60 ps thold = 70 ps tpd = 35 ps tcd = 25 ps tskew = 50 ps

tpd = 3 x 35 ps = 105 ps tcd = 2 x 25 ps = 50 ps Hold time constraint: tccq + tcd > thold + tskew? (30 + 50) ps > (70 ps +50) ps ?

CLK CLK A B C D X' Y' X Y

Add buffers to the shortest paths:

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SLIDE 10

STANDARD MODULES

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SLIDE 11

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Interconnect: Decoder, Encoder, Mux, DeMux

Registers Decoder: Decode the address to assert the addressed device Mux: Select the inputs according to the index addressed by the control signals

P1

Memory Bank

Mux

P2 Pk

Demux

Decoder

Mux

Data Address

Address k Address 2 Address 1 Data 1 Data k

Arbiter

n n-m m 2m

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SLIDE 12

Part III. Standard Modules

Interconnect Modules:

  • 1. Decoder, 2. Encoder
  • 3. Multiplexer, 4. Demultiplexer

12

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SLIDE 13

13

Decoder Definition: A digital module that converts a binary address to the assertion of the addressed device

y0 y1 y7

I0 I1 I2 1 2

1 2 3 4 5 6 7

E (enable) n inputs n= 3 2n outputs 23= 8 yi = 1 if E= 1 & (I2, I1, I0 ) = i yi= 0 otherwise

n to 2n decoder function:

. .

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SLIDE 14

14

  • N inputs, 2N outputs
  • One-hot outputs: only one output HIGH at any

point in time

  • 1. Decoder: Definition

2:4 Decoder A1 A0 Y3 Y2 Y1 Y0 00 01 10 11 1 1 1 1 1 Y3 Y2 Y1 Y0 A0 A1 1 1 1

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SLIDE 15

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Decoder: Logic Diagram (Inside a decoder)

y0 A1’ A0’ y1

En

y3

. .

yi = mi En

y0 = 1 if (A1, A0 ) = (0,0) & En = 1 y7 = A1A0En

2:4 Decoder A1 A0 Y3 Y2 Y1 Y0 00 01 10 11 1 1 1 1 1 Y3 Y2 Y1 Y0 A0 A1 1 1 1

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SLIDE 16

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PI Q: What is the output Y3:0 of the 2:4 decoder for (A1, A0) = (1,0)?

  • A. (1, 1, 0, 0 )
  • B. (1, 0, 1, 1)
  • C. (0, 0, 1, 0)
  • D. (0, 1, 0, 0)
  • 1. Decoder: Definition

2:4 Decoder A1 A0 Y3 Y2 Y1 Y0 00 01 10 11 1 1 1 1 1 Y3 Y2 Y1 Y0 A0 A1 1 1 1

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SLIDE 17

17

  • OR minterms

Implementing functions using Decoders

2:4 Decoder A B 00 01 10 11 Y = AB + AB Y AB AB AB AB Minterm = A ⊕ B

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SLIDE 18

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Decoder Application: universal set {Decoder, OR}

Example: Implement the following functions with a 3-input decoder and OR gates. i) f1(a,b,c) = Σm(1,2,4) ii) f2(a,b,c) = Σm(2,3), iii) f3(a,b,c) = Σm(0,5,6)

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SLIDE 19

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Decoder Application: universal set {Decoder, OR}

Example: Implement the following functions with a 2:4 decoder and OR gates. i) f1(a,b,c) = Σm(1,2,4)

How many 2:4 decoders are required to implement the above function? A. One B. Two C. Three D. Four

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SLIDE 20

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Decoder Application: universal set {Decoder, OR}

Example: Implement the following functions with a 1:2 decoder and OR gates. i) f1(a,b,c) = Σm(1,2,4)

How many 1:2 decoders are required to implement the above function? A. Three B. Four C. Six D. Seven

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SLIDE 21

21

Tree of Decoders

Implement a 4-24 decoder with 3-23 decoders.

I0

y0 y1 y7

I1 I2

1 2 3 4 5 6 7

I0

y8 y9 y15

I1 I2

1 2 3 4 5 6 7

a d c b

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SLIDE 22

22

Implement a 6-26 decoder with 3-23 decoders.

En

D0

I2, I1, I0

D1 y0 y7 y8 y15 D7 y56 y63

En I2, I1, I0 I2, I1, I0 I5, I4, I3

Tree of Decoders

… …

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SLIDE 23

PI Q: A four variable switching function f(a,b,c,d) can be implemented using which of the following?

  • A. 1:2 decoders and OR gates
  • B. 2:4 decoders and OR gates
  • C. 3:8 decoders and OR gates
  • D. None of the above
  • E. All of the above

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SLIDE 24

24

Interconnect: Decoder, Encoder, Mux, DeMux

Processors Decoder: Decode the address to assert the addressed device Mux: Select the inputs according to the index addressed by the control signals

P1

Memory Bank

Mux

P2 Pk

Demux

Decoder

Mux

Data Address

Address k Address 2 Address 1 Data 1 Data k

Arbiter

n n-m m 2m

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SLIDE 25

25

  • 2. Encoder
  • Definition (What is it?)
  • Logic Diagram (How is it realized?)
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SLIDE 26

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  • 2. Encoder: Definition

At most one Ii = 1. (yn-1,.., y0 ) = i if Ii = 1 & En = 1 (yn-1,.., y0 ) = 0 otherwise. A = 1 if En = 1 and one i s.t. Ii = 1 A = 0 otherwise. 8 inputs 3 outputs

y0 y1 y2

1 2 3 4 5 6 7

En A

I0 I7

1 2

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SLIDE 27

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Encoder: Logic Diagram

En I1 I3 I5 I7 y0 En I2 I3 I6 I7 y1 En I4 I5 I6 I7 y2 En I0 I1 I6 I7 A . .

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SLIDE 28

Multiplexer

  • Definition
  • Logic Diagram
  • Application

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SLIDE 29

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Interconnect: Decoder, Encoder, Mux, DeMux

Processors Decoder: Decode the address to assert the addressed device Mux: Select the inputs according to the index addressed by the control signals

P1

Memory Bank

Mux

P2 Pk

Demux

Decoder

Mux

Data Address

Address k Address 2 Address 1 Data 1 Data k

Arbiter

n n-m m 2m

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SLIDE 30

Multiplexer Definition: Example

En y S1 S0

D0 D1 D2 D3

1 2 3

30

S1 S0 y

Selects between one of N inputs to connect to the output. log2N-bit select input – control input

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SLIDE 31

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PI Q: What is the output of the following MUX for the given inputs and En=1, S=1?

  • A. 0
  • B. 1
  • C. Can’t say

En =1 y S=1

1

1

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SLIDE 32

Multiplexer (Mux): Example

2:1 Mux

Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 S D0 Y D1 D1 D0 S Y 1 D1 D0 S

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SLIDE 33

Multiplexer Application

A B Y 1 1 1 1 1 Y = AB

00

Y

01 10 11

A B

  • Mux for a Boolean function with truth table as input

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SLIDE 34

Multiplexer: Application

A B Y 1 1 1 1 1 Y = AB A Y 1 1 A B Y B

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SLIDE 35

Multiplexer Application: universal set {Mux}

Example 1: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with an 8-input Mux.

Id a b c f 0 0 0 0 1 1 0 0 1 1 2 0 1 0 - 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1

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SLIDE 36

Multiplexer Application: universal set {Mux}

Example 1: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with an 8-input Mux.

Id a b c f 0 0 0 0 1 1 0 0 1 1 2 0 1 0 - 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1 En

y

1 1 1

a b c

S2 S1 S0

1 2 3 4 5 6 7 36

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SLIDE 37

En y a b

S1 S0

1 2 3 Example 2: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 4-input Muxes.

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Id a b c f 0 0 0 0 1 1 0 0 1 1 2 0 1 0 - 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1 D (c)

D0 (c) =1 D1 (c) =0 D2 (c) =0 D3 (c) =c

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SLIDE 38

a 1 1 b 1 1 c = 0 1

  • c = 1

1 1 D (c)

D0 (c) =1 D1 (c) =0 D2 (c) =0 D3 (c) =c

En y 1 c a b

S1 S0

1 2 3 Example 2: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 4-input Muxes.

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SLIDE 39

En 1

a

y Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2- input Muxes.

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Id a b c f 0 0 0 0 1 1 0 0 1 1 2 0 1 0 - 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1

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SLIDE 40

D1 (b,c)

b 1 c = 0 c = 1 1 l1(0) = 0 l1(c) = c

En b’ 1

a

y Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2- input Muxes.

40

D0 (b,c) = b’ D1 (b,c) = bc

1

  • 1 0

c b 0 0 0 1 c b

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SLIDE 41

D1 (b,c)

b 1 c = 0 c = 1 1 l1(0) = 0 l1(c) = c

En En b’ 1

a b

y 1 c Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2- input Muxes.

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SLIDE 42
  • 4. Demultiplexers

En x Control Input

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SLIDE 43
  • 4. Demultiplexers

En x y2n-1 -y0 S(n-1,0) Control Input yi = x if i = (Sn-1, .. , S0) & En = 1 yi = 0 otherwise

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SLIDE 44

Shifter

Can be implemented with a mux s d yi

En 1 3 2 1 0

xi+1 xi-1 xi s d xn x0 x-1 xn-1 yn-1 y0

En

s / n l / r yi = xi-1 if En = 1, s = 1, and d = L = xi+1 if En = 1, s = 1, and d = R = xi if En = 1, s = 0 = 0 if En = 0

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SLIDE 45

Barrel Shifter

O or 1 shift O or 2 shift O or 4 shift x s0 s1 s2

y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

shift

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