Lecture 15: Sequential Networks Finite State Machines Moore and - - PowerPoint PPT Presentation

Lecture 15: Sequential Networks – Finite State Machines

Moore and Mealy (contd) CSE 140: Components and Design Techniques for Digital Systems

Diba Mirza

• Dept. of Computer Science and Engineering

University of California, San Diego

1

QUIZ – NO TALKING – NO NOTES Q1: True or False: Can the operation of a NAND gate be implemented using ONLY the following function? Assume you can modify the function by fixing one or more inputs as (1 or 0).

A. True B. No

f(a,b,c)= ab+a’b’ +c

QUIZ – NO TALKING – NO NOTES

Q2: Which of the following functionalities is achieved by the given circuit for the input combination S’R’=(1,0)?

A. Memory: Outputs (Q, Q’) remain unchanged B. Set to zero: (Q, Q’)= (0,1) C. Set to one: (Q, Q’)= (1,0) D. None of the above

QUIZ – NO TALKING – NO NOTES Q3: The following timing diagram corresponds to which of the following latch or flip-flops? (Assume the output is initially 1) CLK Input Output

A. D-latch B. D-flip flop C. T- flip flop D. JK- flip flop

QUIZ – NO TALKING – NO NOTES Q4: Which of the following is true about the given FSM?

• A. It is a Moore machine
• B. It is a Mealy machine with two outputs
• C. It is a Mealy machine that detects the input pattern 0001 in the

input sequence by setting the output to 1

• D. It is a Mealy machine that detects the input pattern 1101 in the

input sequence by setting the output to 1

• E. None of the above

QUIZ – NO TALKING – NO NOTES Q5: For the given Mealy circuit, which of the following is true if x(t) transitions from 1 to 0 at t1 as shown in the following timing diagram ?

• A. Only the state: S(t) can change at t1
• B. Only the output: y(t) can change at t1
• C. y(t) will change at t1 only if S(t) also changes at t1
• D. S(t) and y(t) can only change at the next rising edge of the clock

after t1 C1 C2

CLK x(t) y(t)

Mealy Machine

S(t)

t1 x(t)

7

Mealy implementation of Pattern Recognizer ‘001’

S1 S0

0/0 1/0 0/0 1/1

S2

0/0 1/0 C1 C2

CLK x(t) y(t)

Mealy Machine

S(t)

Q: What information do we need to design C1?

• A. State table showing (current input x(t),

current state S(t) vs. next state, S(t+1))

• B. State table showing (current input, current

state vs. current output y(t))

• C. State table showing (current input, current

state vs. current output y(t) and next state)

• D. None of the above

8

State Diagram => State Table with State Assignment

State Assignment S0: 00 S1: 01 S2: 10

S(t)\x 1 S0 S1,0 S0,0 S1 S2,0 S0,0 S2 S2,0 S0,1

S(t)\x 1 00 01,0 00,0 01 10,0 00,0 10 10,0 00,1 Q1(t+1)Q0(t+1), y

S1 S0

0/0 1/0 0/0 1/1

S2

0/0 1/0 C1 C2

CLK x(t) y(t)

Mealy Machine

S(t)

9

State Diagram => State Table => Excitation Table => Circuit

Q1(t) Q0(t)\x 0 1 00 01,0 00,0 01 10,0 00,0 10 10,0 00,1

id Q1Q0x D1 D0 y 000 1 1 001 2 010 1 3 011 4 100 1 5 101 1 6 110 X X X 7 111 X X X C1 C2

CLK x(t) y(t)

Mealy Machine

S(t)

10

0 2 6 4 1 3 7 5

x(t) Q1

0 1 X 1 0 0 X 0

Q0

D1(t): D1(t) = x’Q0 + x’Q1 D0 (t)= Q’1Q’0 x’ y= Q1x State Diagram => State Table => Excitation Table => Circuit id Q1Q0x D1 D0 y 000 1 1 001 2 010 1 3 011 4 100 1 5 101 1 6 110 X X X 7 111 X X X

11

D Q Q’ D Q Q’

Q1 Q0 D1 D0 Q0 Q1 x’ D1(t) = x’Q0 + x’Q1 D0 (t)= Q’1Q’0 x’ y= Q1x x y Q’1 Q’0 x’ State Diagram => State Table => Excitation Table => Circuit C1 C2

CLK x(t) y(t)

Mealy Machine

S(t)

12

D Q Q’ D Q Q’

Q1 Q0 D1 D0 Q0 Q1 x’ x y Q’1 Q’0 x’

State Diagram => State Table => Excitation Table => Netlist S1 S0

0/0 1/0 0/0 1/1

S2

0/0 1/0

iClicker: The relation between the above state diagram and sequential circuit.

• A. One to one.
• B. One to many
• C. None of the above