Instruction Set Architecture Assembly Language View Computer - PDF document

Instruction Set Architecture Assembly Language View Computer Architecture: Instruction Set ◼ Processor state Application Program ⚫ Registers, memory, … Architecture ◼ Instructions Compiler OS ⚫ addq , pushq , ret , … ⚫ How instructions are encoded ISA CSci 2021: Machine Architecture and Organization as bytes March 18th-20th, 2018 CPU Layer of Abstraction Design Your instructor: Stephen McCamant ◼ Above: how to program machine Circuit ⚫ Processor executes instructions Design Based on slides originally by: in a sequence Randy Bryant, Dave O’Hallaron Chip ◼ Below: what needs to be built Layout ⚫ Use variety of tricks to make it run fast ⚫ E.g., execute multiple – 1 – – 2 – CS:APP3e instructions simultaneously CS:APP3e 1 2 Y86-64 Processor State Y86-64 Instruction Set #1 Byte 0 1 2 3 4 5 6 7 8 9 RF: Program CC: Stat: Program status halt 0 0 registers Condition codes %rax %rsp %r8 %r12 DMEM: Memory nop 1 0 %rcx %rbp %r9 %r13 ZF SF OF %rdx %rsi %r10 %r14 PC %rbx %rdi %r11 cmovXX rA , rB 2 fn rA rB irmovq V , rB 3 0 F rB V ◼ Program Registers ⚫ 15 registers (omit %r15 ). Each 64 bits rmmovq rA , D ( rB ) 4 0 rA rB D ◼ Condition Codes mrmovq D ( rB ), rA 5 0 rA rB D ⚫ Single-bit flags set by arithmetic or logical instructions OPq rA , rB 6 » ZF: Zero SF: Negative OF: Overflow fn rA rB ◼ Program Counter jXX Dest 7 fn Dest ⚫ Indicates address of next instruction call Dest 8 0 Dest ◼ Program Status ret 9 0 ⚫ Indicates either normal operation or some error condition ◼ Memory pushq rA A 0 F rA ⚫ Byte-addressable storage array popq rA B 0 F rA – 3 – – 4 – CS:APP3e CS:APP3e ⚫ Words stored in little-endian byte order 3 4 Y86-64 Instructions Y86-64 Instruction Set #2 rrmovq 2 0 0 1 2 3 4 5 6 7 8 9 Byte cmovle 2 1 halt 0 0 Format cmovl 2 2 ◼ 1 – 10 bytes of information read from memory nop 1 0 ⚫ Can determine instruction length from first byte cmove 2 3 cmovXX rA , rB 2 fn rA rB ⚫ Not as many instruction types, and simpler encoding than with cmovne 2 4 irmovq V , rB 3 0 F x86-64 rB V cmovge 2 5 ◼ Each accesses and modifies some part(s) of the program rmmovq rA , D ( rB ) 4 0 rA rB D state cmovg 2 6 mrmovq D ( rB ), rA 5 0 rA rB D OPq rA , rB 6 fn rA rB jXX Dest 7 fn Dest call Dest 8 0 Dest ret 9 0 pushq rA A 0 rA F popq rA B 0 F rA – 5 – CS:APP3e – 6 – CS:APP3e 5 6

Y86-64 Instruction Set #3 Y86-64 Instruction Set #4 Byte 0 1 2 3 4 5 6 7 8 9 Byte 0 1 2 3 4 5 6 7 jmp 8 9 7 0 halt 0 0 halt 0 0 jle 7 1 nop 1 0 nop 1 0 jl 7 2 cmovXX rA , rB 2 cmovXX rA , rB 2 fn rA rB fn rA rB je 7 3 irmovq V , rB 3 0 F irmovq V , rB 3 0 F rB V rB V jne 7 4 rmmovq rA , D ( rB ) 4 0 rA rB D rmmovq rA , D ( rB ) 4 0 rA rB D jge 7 5 addq 6 0 mrmovq D ( rB ), rA 5 0 mrmovq D ( rB ), rA 5 0 rA rB D rA rB D jg 7 6 subq 6 1 OPq rA , rB 6 OPq rA , rB 6 fn rA rB fn rA rB andq 6 2 jXX Dest 7 jXX Dest 7 fn Dest fn Dest xorq 6 3 call Dest 8 0 call Dest 8 0 Dest Dest ret 9 0 ret 9 0 pushq rA A 0 F pushq rA A 0 F rA rA popq rA B 0 F popq rA B 0 F rA rA – 7 – – 8 – CS:APP3e CS:APP3e 7 8 Encoding Registers Instruction Example Each register has a 4-bit ID Addition Instruction Generic Form %rax 0 %r8 8 %rcx 1 %r9 9 %rdx 2 %r10 A Encoded Representation %rbx 3 %r11 B %rsp 4 %r12 C addq rA , rB 6 0 rA rB %rbp 5 %r13 D %rsi 6 %r14 E %rdi 7 F No Register ◼ Add value in register rA to that in register rB ◼ Same encoding as in x86-64 ⚫ Store result in register rB Register ID 15 ( 0xF ) indicates “no register” ⚫ Note that Y86-64 only allows addition to be applied to register data ◼ Will use this in our hardware design in multiple places ◼ Set condition codes based on result ◼ e.g., addq %rax,%rsi Encoding: 60 06 ◼ Two-byte encoding ⚫ First indicates instruction type ⚫ Second gives source and destination registers – 9 – – 10 – CS:APP3e CS:APP3e 9 10 Arithmetic and Logical Operations Move Operations Register ➔ Register Instruction Code Function Code ◼ Refer to generically as Add rrmovq rA , rB 2 0 “ OPq ” addq rA , rB 6 0 rA rB ◼ Encodings differ only by Immediate ➔ Register “function code” irmovq V , rB 3 0 F rB V Subtract (rA from rB) ⚫ Low-order 4 bits in first instruction word Register ➔ Memory subq rA , rB 6 1 rA rB ◼ Set condition codes as rmmovq rA , D ( rB) 4 0 rA rB D And side effect Memory ➔ Register 6 2 rA rB andq rA , rB mrmovq D ( rB), rA 5 0 rA rB D Exclusive-Or xorq rA , rB 6 3 rA rB ◼ Like the x86-64 movq instruction ◼ Simpler format for memory addresses ◼ Give different names to keep them distinct – 11 – CS:APP3e – 12 – CS:APP3e 11 12

Move Instruction Examples Conditional Move Instructions Move Unconditionally X86-64 Y86-64 2 0 rA rB ◼ Refer to generically as rrmovq rA, rB movq $0xabcd, %rdx irmovq $0xabcd, %rdx “ cmovXX ” Move When Less or Equal 30 82 cd ab 00 00 00 00 00 00 Encoding: ◼ Encodings differ only by cmovle rA, rB 2 1 rA rB “function code” Move When Less movq %rsp, %rbx rrmovq %rsp, %rbx ◼ Based on values of 2 2 rA rB cmovl rA, rB 20 43 condition codes Encoding: Move When Equal ◼ Variants of rrmovq movq -12(%rbp),%rcx mrmovq -12(%rbp),%rcx cmove rA, rB 2 3 rA rB instruction 50 15 f4 ff ff ff ff ff ff ff ⚫ (Conditionally) copy value Encoding: Move When Not Equal from source to destination 2 4 rA rB cmovne rA, rB movq %rsi,0x41c(%rsp) rmmovq %rsi,0x41c(%rsp) register Move When Greater or Equal 40 64 1c 04 00 00 00 00 00 00 Encoding: cmovge rA, rB 2 5 rA rB Move When Greater 2 6 rA rB cmovg rA, rB – 13 – – 14 – CS:APP3e CS:APP3e 13 14 Jump Instructions Jump Instructions Jump (Conditionally) Jump Unconditionally jXX Dest 7 fn jmp Dest 7 0 Dest Dest Jump When Less or Equal jle Dest 7 1 Dest ◼ Refer to generically as “ jXX ” Jump When Less ◼ Encodings differ only by “function code” fn jl Dest 7 2 Dest ◼ Based on values of condition codes Jump When Equal ◼ Same as x86-64 counterparts je Dest 7 3 Dest ◼ Encode full destination address Jump When Not Equal ⚫ Unlike PC-relative addressing seen in x86-64 jne Dest 7 4 Dest Jump When Greater or Equal jge Dest 7 5 Dest Jump When Greater jg Dest 7 6 Dest – 15 – – 16 – CS:APP3e CS:APP3e 15 16 Y86-64 Program Stack Stack Operations Stack “Bottom” ◼ Region of memory holding pushq rA A 0 rA F program data ◼ Used in Y86-64 (and x86-64) for ◼ Decrement %rsp by 8 supporting procedure calls ◼ Store word from rA to memory at %rsp ◼ Stack top indicated by %rsp ◼ Like x86-64 • ⚫ Address of top stack element Increasing • ◼ Stack grows toward lower popq rA B 0 rA F Addresses addresses • ⚫ Top element is at highest address in the stack ◼ Read word from memory at %rsp ⚫ When pushing, must first ◼ Save in rA decrement stack pointer ◼ Increment %rsp by 8 ⚫ After popping, increment stack %rsp ◼ Like x86-64 pointer Stack “Top” – 17 – CS:APP3e – 18 – CS:APP3e 17 18

Subroutine Call and Return Miscellaneous Instructions call Dest 8 0 nop 1 0 Dest ◼ Don’t do anything ◼ Push address of next instruction onto stack ◼ Start executing instructions at Dest ◼ Like x86-64 0 0 halt ◼ Stop executing instructions ret 9 0 ◼ x86-64 has comparable instruction, but can’t execute it in user mode ◼ Pop value from stack ◼ We will use it to stop the simulator ◼ Use as address for next instruction ◼ Encoding ensures that program hitting memory ◼ Like x86-64 initialized to zero will halt – 19 – – 20 – CS:APP3e CS:APP3e 19 20 Status Conditions Writing Y86-64 Code Mnemonic Code ◼ Normal operation Try to Use C Compiler as Much as Possible AOK 1 ◼ Write code in C ◼ Compile for x86-64 with gcc – Og – S ◼ Halt instruction encountered Mnemonic Code ◼ Transliterate into Y86-64 HLT 2 ◼ Modern compilers make this more difficult, alas ◼ Bad address (either instruction or data) Mnemonic Code encountered ADR 3 Coding Example ◼ Invalid instruction encountered Mnemonic Code ◼ Find number of elements in null-terminated list INS 4 long len1(long a[]); a 5043 Desired Behavior 6125  3 ◼ If AOK, keep going 7395 ◼ Otherwise, stop program execution 0 – 21 – – 22 – CS:APP3e CS:APP3e 21 22 Y86-64 Code Generation Example Y86-64 Code Generation Example #2 First Try Problem Second Try Result ◼ Write typical array code ◼ Hard to do array indexing on ◼ Write C code that mimics ◼ Compiler generates exact expected Y86-64 code Y86-64 same code as before! ⚫ Since don’t have scaled ◼ Compiler converts both long len2(long *a) /* Find number of elements in addressing modes versions into same { null-terminated list */ intermediate form L3: long ip = (long) a; long len(long a[]) addq $1,%rax long val = *(long *) ip; { cmpq $0, (%rdi,%rax,8) long len = 0; long len; jne L3 while (val) { for (len = 0; a[len]; len++) ip += sizeof(long); ; len++; return len; val = *(long *) ip; } } return len; ◼ Compile with gcc -Og -S } – 23 – CS:APP3e – 24 – CS:APP3e 23 24