Lecture 3: Instruction Lecture 3: Instruction of a computer that a - - PDF document

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Lecture 3: Instruction Lecture 3: Instruction of a computer that a - - PDF document

Jan 12, 2023 130 likes •188 views

What Is ISA? What Is ISA? Instruction set architecture is the structure Instruction set architecture is the structure Lecture 3: Instruction Lecture 3: Instruction of a computer that a machine language of a computer that a machine language

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Lecture 3: Instruction Lecture 3: Instruction Set Architecture Set Architecture

ISA types, register usage, ISA types, register usage, memory addressing, memory addressing, endian endian and alignment, quantitative and alignment, quantitative evaluation evaluation

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What Is ISA? What Is ISA?

Instruction set architecture is the structure Instruction set architecture is the structure

  • f a computer that a machine language
  • f a computer that a machine language

programmer (or a compiler) must programmer (or a compiler) must understand to write a correct (timing understand to write a correct (timing independent) program for that machine. independent) program for that machine. For IBM System/360, 1964 For IBM System/360, 1964

  • Class ISA types: Stack, Accumulator, and

Class ISA types: Stack, Accumulator, and General General-

  • purpose register

purpose register

  • ISA is mature and stable

ISA is mature and stable

– – Why do we study it? Why do we study it?

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Stack Stack

Implicit operands on stack

  • Ex. C = A + B

Push A Push B Add Pop C Good code density; used in 60’s-70’s; now in Java VM

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Accumulator Accumulator

  • The accumulator provides an

The accumulator provides an implicit input, and is the implicit input, and is the implicit place to store the implicit place to store the result. result.

  • Ex. C = A + B
  • Ex. C = A + B

Load R1, A Load R1, A Add R3, R1, B Add R3, R1, B Store R3, c Store R3, c

  • Used before 1980

Used before 1980

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General General-

  • purpose Registers

purpose Registers

  • General

General-

  • purpose registers are preferred by

purpose registers are preferred by compilers compilers

– – Reduce memory traffic Reduce memory traffic – – Improve program speed Improve program speed – – Improve code density Improve code density

  • Usage of general

Usage of general-

  • purpose registers

purpose registers

– – Holding temporal variables in expression evaluation Holding temporal variables in expression evaluation – – Passing parameters Passing parameters – – Holding variables Holding variables

  • GPR and RISC and CISC

GPR and RISC and CISC

– – RISC ISA is extensively used for desktop, server, and RISC ISA is extensively used for desktop, server, and embedded: MIPS, PowerPC, embedded: MIPS, PowerPC, UltraSPARC UltraSPARC, ARM, MIPS16, , ARM, MIPS16, Thumb Thumb – – CISC: IBM 360/370, VAX, and Intel 80x86 CISC: IBM 360/370, VAX, and Intel 80x86

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Variants of GRP Architecture Variants of GRP Architecture

  • Number of operands in ALU instructions: two or

Number of operands in ALU instructions: two or three three

Add R1, R2, R3 Add R1, R2, R3 Add R1, R2 Add R1, R2

  • Maximal number of memory operands in ALU

Maximal number of memory operands in ALU instructions: zero, one, two, or three instructions: zero, one, two, or three

Load R1, A Load R1, A Load R1, A Load R1, A Load R2, B Load R2, B Add R3, R1, B Add R3, R1, B Add R3, R1, R2 Add R3, R1, R2

  • Three popular combinations

Three popular combinations

– – register register-

  • register (load

register (load-

  • store): 0 memory, 3 operands

store): 0 memory, 3 operands – – register register-

  • memory: 1 memory, 2 operands

memory: 1 memory, 2 operands – – memory memory-

  • memory: 2 memories, 2 operands; or 3

memory: 2 memories, 2 operands; or 3 memories, 3 operands memories, 3 operands

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Register Register-

  • memory

memory

  • There is no implicit

There is no implicit

  • perand
  • perand
  • One input operand is

One input operand is register, and one in register, and one in memory memory

  • Ex. C = A + B
  • Ex. C = A + B

Load R1, A Load R1, A Add R3, R1, B Add R3, R1, B Store R3, C Store R3, C

  • Processors include VAX,

Processors include VAX, 80x86 80x86

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Register Register-

  • register (Load

register (Load-

  • store)

store)

  • Both operands are registers

Both operands are registers

  • Values in memory must be

Values in memory must be loaded into a register and loaded into a register and stored back stored back

  • Ex. C = A + B
  • Ex. C = A + B

Load R1, A Load R1, A Load R2, B Load R2, B Add R3, R1, R2 Add R3, R1, R2 Store R3, C Store R3, C

  • Processors: MIPS, SPARC

Processors: MIPS, SPARC

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How Many Registers? How Many Registers?

If the number of registers increase: If the number of registers increase:

  • Allocate more variables in registers (fast

Allocate more variables in registers (fast accesses) accesses)

  • Reducing code spill

Reducing code spill

  • Reducing memory traffic

Reducing memory traffic

  • Longer register

Longer register specifiers specifiers (difficult encoding) (difficult encoding)

  • Increasing register access time (physical

Increasing register access time (physical registers) registers)

  • More registers to save in context switch

More registers to save in context switch MIPS64: 32 general MIPS64: 32 general-

  • purpose registers

purpose registers

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ISA and Performance ISA and Performance

CPU time = #inst × CPI × cycle time CPU time = #inst × CPI × cycle time

  • RISC with Register

RISC with Register-

  • Register instructions

Register instructions

  • Simple, fix

Simple, fix-

  • length instruction encoding

length instruction encoding

  • Simple code generation

Simple code generation

  • Regularity in CPI

Regularity in CPI

  • Higher instruction counts

Higher instruction counts

  • Lower instruction density

Lower instruction density

  • CISC with Register

CISC with Register-

  • memory instructions

memory instructions

  • No extra load in accessing data in memory

No extra load in accessing data in memory

  • Easy encoding

Easy encoding

  • Operands being not equivalent

Operands being not equivalent

  • Restricted #registers due to encoding memory address

Restricted #registers due to encoding memory address

  • Irregularity in CPI

Irregularity in CPI

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Memory Addressing Memory Addressing

Instructions see registers, constant values, and memory Instructions see registers, constant values, and memory

  • Addressing mode

Addressing mode decides how to specify an object to access decides how to specify an object to access

– – Object can be memory location, register, or a constant Object can be memory location, register, or a constant – – Memory addressing is complicated Memory addressing is complicated

  • Memory addressing

Memory addressing involves many factors involves many factors

– – Memory addressing mode Memory addressing mode – – Object size Object size – – byte ordering byte ordering – – alignment alignment

For a memory location, its For a memory location, its effective address effective address is calculated in a is calculated in a certain form of register content, immediate address, and certain form of register content, immediate address, and PC, as specified by the addressing mode PC, as specified by the addressing mode

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Little or Big: Where to Start? Little or Big: Where to Start?

  • Byte ordering:

Byte ordering: Where is the first Where is the first byte? byte?

  • Big

Big-

  • endian

endian: :IBM IBM, , SPARC, SPARC, Mororola Mororola

  • Little

Little-

  • endian: Intel,

endian: Intel, DEC DEC

  • Supporting both:

Supporting both: MIPS, PowerPC MIPS, PowerPC

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00000000 Big-endian Little-endian

Number 0x5678

00000001 00000002 00000003

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Alignment Alignment

Align n Align n-

  • byte objects on n

byte objects on n-

  • byte

byte boundaries (n = 1, 2, 4, 8) boundaries (n = 1, 2, 4, 8)

  • One align position, n

One align position, n-

  • 1 misaligned

1 misaligned positions positions

  • Misaligned access is

Misaligned access is undiserable undiserable

– – Expensive logic, slow references Expensive logic, slow references

  • Aligning in registers may be

Aligning in registers may be necessary for bytes and half words necessary for bytes and half words

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MIPS Data Addressing Modes MIPS Data Addressing Modes

  • Register

Register

ADD $16, $7, $8 ADD $16, $7, $8

  • Immediate

Immediate

ADDI $17, $7, ADDI $17, $7, 100 100

  • Displacement

Displacement

LW $18, 100($9) LW $18, 100($9) Only the three are supported for data addressing Only the three are supported for data addressing

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Storage Used by Compilers Storage Used by Compilers

Register storage Register storage

– – Holding temporal variables in expression Holding temporal variables in expression evaluation evaluation – – Passing parameters Passing parameters – – Holding variables Holding variables

Memory storages consists of Memory storages consists of

– – Stack: to hold local variables Stack: to hold local variables – – Global data area: to hold statically declared Global data area: to hold statically declared

  • bjects
  • bjects

– – Heap: to hold dynamic objects Heap: to hold dynamic objects

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Memory Addressing Seen in Memory Addressing Seen in CISC CISC

  • Direct (absolute)

Direct (absolute)

  • Register indirect

Register indirect

  • Indexed

Indexed

  • Scaled

Scaled

  • Autoincrement

Autoincrement

  • Autodecrement

Autodecrement

  • Memory indirect

Memory indirect And more … And more … ADD R1, (1001) ADD R1, (1001) SUB R2, (R1) SUB R2, (R1) ADD R1, (R2 + R3) ADD R1, (R2 + R3) SUB R2, SUB R2, 100(R2)[R3] 100(R2)[R3] ADD R1, (R2)+ ADD R1, (R2)+ SUB R2, SUB R2, -

  • (R1)

(R1) ADD R1, @(R3) ADD R1, @(R3) (see textbook p98) (see textbook p98)

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Choosing of Memory Addressing Choosing of Memory Addressing Modes Modes

Choosing complex addressing modes Choosing complex addressing modes

  • Close to addressing in high

Close to addressing in high-

  • level language

level language

  • May reduce instruction counts (thus fast)

May reduce instruction counts (thus fast)

  • Increase implementation complexity (may

Increase implementation complexity (may increase cycle time) increase cycle time)

  • Increase CPI

Increase CPI RISC ISA comes with simple memory RISC ISA comes with simple memory addressing, and CISC ISA with complex addressing, and CISC ISA with complex

  • nes
  • nes

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How Often Are Those Address How Often Are Those Address Modes? Modes?

Usage of address modes, VAX machine, SPEC89

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Usage of Immediate Operands In Usage of Immediate Operands In RISC RISC

Alpha, SPEC CINT2000 & CFP2000

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Immediate Size in RISC Immediate Size in RISC

Alpha, SPEC CINT2000 & CFP2000

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Displacement Size in RISC Displacement Size in RISC

Displacement bit size: Alpha ISA, SPEC CPU2000 Integer and FP

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Operands size, type and format Operands size, type and format

  • In MIPS

In MIPS Opcode Opcode encodes operand size encodes operand size

– – Ex. ADD for signed integer, ADDU for unsigned integer,

  • Ex. ADD for signed integer, ADDU for unsigned integer,

ADD.D for double ADD.D for double-

  • precision FP

precision FP

  • Most common types include

Most common types include

– – Integer: complement binary numbers Integer: complement binary numbers – – Character: ASCII Character: ASCII – – Floating point: IEEE standard 754, single Floating point: IEEE standard 754, single-

  • precision or

precision or double double-

  • precision

precision

  • Decimal format

Decimal format

– – 4 4-

  • bits for one decimal digit (0

bits for one decimal digit (0-

  • 9), one byte for two

9), one byte for two decimal digits decimal digits – – Necessary for business applications Necessary for business applications

  • Fixed Point format in DSP processors:

Fixed Point format in DSP processors:

– – Representing fractions in ( Representing fractions in (-

  • 1, +1)

1, +1) – – 11000101 11000101fixed point

fixed point=

= -

  • 0.1000101

0.10001012

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Dynamic Instruction Mix (MIPS) Dynamic Instruction Mix (MIPS)

SPEC2K SPEC2K Int Int SPEC2K FP SPEC2K FP Load Load 26% 26% 15% 15% Store Store 10% 10% 2% 2% Add Add 19% 19% 23% 23% Compare Compare 5% 5% 2% 2% Cond Cond br br 12% 12% 4% 4% Cond Cond mv mv 2% 2% 0% 0% Jump Jump 1% 1% 0% 0% LOGIC LOGIC 18% 18% 4% 4% FP load FP load 15% 15% FP store FP store 7% 7% FP others FP others 19% 19%

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Compiler Effects Compiler Effects

Architectures change for the needs of compilers

  • How do compilers use registers? How many?
  • How do compilers use addressing modes?
  • Anything that compilers do not like?