Virtual Memory II Philipp Koehn 11 November 2019 Philipp Koehn - PowerPoint PPT Presentation

Virtual Memory II Philipp Koehn 11 November 2019 Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Address Space 1 N = 2 n bytes • Virtual memory size: M = 2 m bytes • Physical memory size: P = 2 p bytes • Page (block of memory): • A virtual address can be encoded in n bits Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Address Translation 2 • Task: mapping virtual address to physical address – virtual address (VA): used by machine code instructions – physical address (PA): location in RAM • Formally MAP: VA → PA ∪ 0 where: MAP(A) = PA if in RAM xxxxx = 0 otherwise • Note: this happens very frequently in machine code • We will do this in hardware: Memory Management Unit (MMU) Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Basic Architecture 3 Virtual address page table base register Physical address Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Basic Architecture 4 Virtual address Valid Physical page number page table base register Physical address Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Basic Architecture 5 Virtual address virtual page number page o ff set Valid Physical page number page table base register physical page number page o ff set Physical address Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Basic Architecture 6 Virtual address virtual page number page o ff set Valid Physical page number page table base register valid = 0? -> page fault physical page number page o ff set Physical address Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Page Hit 7 CPU chip PTEA PTE VA CPU MMU Memory PA Data • VA: CPU requests data at virtual address • PTEA: look up page table entry in page table • PTE: returns page table entry • PA: get physical address from entry, look up in memory • Data: returns data from memory to CPU Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Page Fault 8 Exception Page fault exception handler CPU chip PTEA PTE VA CPU MMU Memory Data • VA: CPU requests data at virtual address • PTEA: look up page table entry in page table • PTE: returns page table entry • Exception: page not in physical memory Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Page Fault 9 Exception Page fault exception handler CPU chip PTEA Victim page PTE New page VA CPU MMU Memory Disk Data • VA: CPU requests data at virtual address • PTEA: look up page table entry in page table • PTE: returns page table entry • Exception: page not in physical memory • Page fault exception handler – victim page to disk – new page to memory – update page table entries Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Page Fault 10 Exception Page fault exception handler CPU chip PTEA Victim page PTE New page VA CPU MMU Memory Disk PA Data • VA: CPU requests data at virtual address • PTEA: look up page table entry in page table • PTE: returns page table entry • Exception: page not in physical memory • Page fault exception handler – victim page to disk – new page to memory – update page table entries • Re-do memory request Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Page Miss Exception 11 • Complex task – identify which page to remove from RAM (victim page) – load page from disk to RAM – update page table entry – trigger do-over of instruction that caused exception • Note – loading into RAM very slow – added complexity of handling in software no big deal Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Refinements 12 • On-CPU cache → integrate cache and virtual memory • Slow look-up time → use translation lookahead buffer (TLB) • Huge address space → multi-level page table • Putting it all together Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Refinements 13 • On-CPU cache → integrate cache and virtual memory • Slow look-up time → use translation lookahead buffer (TLB) • Huge address space → multi-level page table • Putting it all together Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Integrating Caches and Virtual Memory 14 • Note – we claim that using on-disk memory is too slow – having data in RAM only practical solution • Recall – we previously claimed that using RAM is too slow – having data in cache only practical solution • Both true, so we need to combine Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Integrating Caches and Virtual Memory 15 CPU chip PTEA PTE L1 VA CPU MMU Cache DRAM PA Data • MMU resolves virtual address to physical address • Physical address is checked against cache Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Integrating Caches and Virtual Memory 16 CPU chip PTEA miss? PTEA PTE PTE L1 VA CPU MMU Cache DRAM PA Data • Cache miss in page table retrieval? ⇒ Get page table from memory Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Integrating Caches and Virtual Memory 17 CPU chip PTEA miss? PTEA PTE PTE L1 VA CPU MMU Cache DRAM PA miss? PA Data Data • Cache miss in data retrieval? ⇒ Get data from memory Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Refinements 18 • On-CPU cache → integrate cache and virtual memory • Slow look-up time → use translation lookahead buffer (TLB) • Huge address space → multi-level page table • Putting it all together Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Look-Ups 19 • Every memory-related instruction must pass through MMU (virtual memory look-up) • Very frequent, this has to be very fast • Locality to the rescue – subsequent look-ups in same area of memory – look-up for a page can be cached Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Translation Lookup Buffer 20 • Same structure as cache • Break up address into 3 parts – lowest bits: offset in page – middle bits: index (location) in cache – highest bits: tag in cache • Associative cache: more than one entry per index Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Architecture 21 CPU chip TLB VA CPU MMU Memory PA Data • Translation lookup buffer (TLB) on CPU chip Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Translation Lookup Buffer (TLB) Hit 22 CPU chip TLB PTEA PTE VA CPU MMU Memory PA Data • Look up page table entry in TLB Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Translation Lookup Buffer (TLB) Miss 23 CPU chip TLB PTEA PTE PTEA VA CPU MMU Memory PA Data • Page table entry not in TLB • Retrieve page table entry from RAM Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Refinements 24 • On-CPU cache → integrate cache and virtual memory • Slow look-up time → use translation lookahead buffer (TLB) • Huge address space → multi-level page table • Putting it all together Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Page Table Size 25 • Example – 32 bit address space: 4GB – Page size: 4KB – Size of page table entry: 4 bytes → Number of pages: 1M → Size of page table: 4MB • Recall: one page table per process • Very wasteful: most of the address space is not used Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

2-Level Page Table 26 Level 1 Level 2 Physical page table page table memory Valid Physical page PTE 0 Valid Level 2 page table L2 PT 0 PTE 1023 L2 PT 1 null null Valid Physical page null PTE 0 null null null PTE 1023 L2 PT 8 null Valid Physical page null PTE 1023 Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Multi-Level Page Table 27 • Our example: 1M entries • 2-level page table → each level 1K entry (1K 2 =1M) • 4-level page table → each level 32 entry (32 4 =1M) Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Refinements 28 • On-CPU cache → integrate cache and virtual memory • Slow look-up time → use translation lookahead buffer (TLB) • Huge address space → multi-level page table • Putting it all together Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019

Virtual Address 29 CPU RAM Data Virtual address VPN VPO L1 hit L1 miss TLBT TLBI TLB L1 Cache TLB hit … … TLB miss VPN1 VPN2 VPN3 VPN4 PPN PPO CT CI CO CR3 PTE PTE PTE PTE Philipp Koehn Computer Systems Fundamentals: Virtual Memory II 11 November 2019