Roadmap 1. Instruction Set Architectures (ISA) What is CISC? What - PowerPoint PPT Presentation

Roadmap 1. Instruction Set Architectures (ISA) What is CISC? What is RISC? Why did RISC prevail in the instruction set “wars”? Describe a simple RISC ISA called DLX 2. Designing a simple DLX processor: Single Cycle Implementation Multiple Cycle Implementation Lead to Pipelined Processor Design

CISC and RISC 1. What is CISC? Complex Instruction Set Computer 2. What is RISC? Reduced Instruction Set Computer

CISC Rich (complex) Instruction Set Architecture • Complex Instructions – Procedure Call : Set up Stack Frame, Save Registers , Transfer Control – Block Copy: Transfer n bytes from source address to destination address • Specialized instructions – String Manipulation – Multiprecision decimal arithmetic • Complex Addressing modes – Access a field in the i th record of an array of structs – Access array element in a stack frame (base, index, scale factors, offset) – Multiple levels of indirection in dereferencing a pointer • Variable Length Instructions – 1 - 18 bytes in x86 • Irregular Complicated Instruction formats

Why CISC? Technological and Philosophical • Fewer number of executed instructions in program – Each instruction does more work – Reduce costly memory accesses for instruction fetch • Reduce Semantic Gap – ISA matches the constructs of high-level languages – Compiler less complicated • Reduce Code Memory Footprint – Saves expensive memory Question: What are we giving up to get those benefits. Tradeoffs?

Why CISC? Execution Time (in seconds) = Number of instructions x Average number of Cycles/Instruction x Sec/Cycle = N x CPI / Clock Frequency • CISC concentrates on reducing N • Would we be better off if we traded off bigger N for lower CPI and higher clock rate? • Empirical studies show that roughly 20% of available instructions used in typical programs – Compilers and programmers were not widely using the specialized, complex instructions – Semantic mismatch

RISC ISA Less is More! Keep It Simple • Simple General-Purpose Instructions • Simple Addressing Modes • Fixed Length Instructions • Fixed Format Instructions (fields in instructions have fixed meaning) Enables High Performance • Simple and fast hardware implementation • Simple regular abstract interface to compiler • Expose micro architecture features to software • Structured use of concurrency in micro architecture

RISC ISA • Many General Purpose Registers • Pipelining • Caches • Compiler Optimization CISC vs RISC Debate: Conclusively settled (at least till technology changes) What about Intel x86 processors?

ISA: Operations • Integer Arithmetic/Logical Operations (ALU ops) – ADD, SUB, MUL, AND, OR, NOT …. • Data Transfer : – Register-Register Copy – Load, Store (between memory and registers) • Control Flow: – Branch (conditional), Jump, Procedure Call, Return, Trap • System: Trap (OS Calls), Control (internal hardware) • Floating Point: Floating Point Operations • Special: Decimal, String, Media, Graphics [SPECint92 study on 80x86]: 10 instructions make up 96% executed instructions OPERANDS 1 - 8 bytes depending on type (char, int, float, double etc)

ISA: Addressing Modes Architectures with Implicit Addressing Modes Example : MEM[C] = MEM[A] + MEM[B] 1. Accumulator Architecture: (Older, Low-end embedded microcontrollers) • 1 operand /result is implicitly in a special Accumulator register LOAD A | ACC = MEM[A] ADD B | ACC = ACC + MEM[B] STORE C | MEM[C] = ACC 2. Stack Architecture : (JVM, hardware supported obsolete) Operand(s) / result implicitly on top of the stack PUSH A | STACK[top--] = MEM[A] PUSH B | STACK[top--] = MEM[B] ADD | T1 = STACK[++top];T2 = STACK[++top]; STACK[top--] = T1 + T2 POP C | MEM[C] = STACK[++top]

ISA: Addressing Modes Architectures with Explicitly Addressed Operands Operands either in registers or in memory Example: MEM[C] = MEM[A] + MEM[B] 1. Load/Store Architecture: (MIPS and other RISC processors) • Register Operands only LOAD R1, A | R1 = MEM[A] LOAD R2, B | R2 = MEM[B] ADD R3, R1, R2 | R3 = R1 + R2 STORE R3, C | MEM[C] = R3 + Fixed-Length Encoding - Higher Instruction Count + Simple Code Generation - Larger memory Footprint + Uniform Execution Time

ISA: Addressing Modes Architectures with Explicitly Addressed Operands Operands either in registers or in memory Example: MEM[C] = MEM[A] + MEM[B] 2. Register-Memory Architecture: (IBM 360/370, Intel x86, M68xxx, TI TMS320C54x) 1 Operand is in memory LOAD R1, A | R1 = MEM[A] ADD R1, R1, B | R1 = R1 + MEM[B] STORE R1, C | MEM[C] = R1 3. Memory-Memory Architecture : (VAX) Not in use today 2 or 3 memory operands per instruction ADD A, A, B ADD C, A, B + Compact Code - Long instruction size + Good register availability - Memory Access bottleneck