LLVM IR and the IoT Dvid Juhsz david.juhasz@imsystech.com 4/2/2018 - - PowerPoint PPT Presentation

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Dec 11, 2022 204 likes •440 views

A unique processor architecture meeting LLVM IR and the IoT Dvid Juhsz david.juhasz@imsystech.com 4/2/2018 1 FOSDEM 2018 LLVM devroom Compiling with LLVM High-Level Programming Language LLVM LLVM Front-end LLVM Assembly / IR LLVM

SLIDE 1

A unique processor architecture meeting LLVM IR and the IoT

Dávid Juhász david.juhasz@imsystech.com

4/2/2018 FOSDEM 2018 LLVM devroom 1

SLIDE 2

Compiling with LLVM

4/2/2018 FOSDEM 2018 LLVM devroom 2

LLVM

High-Level Programming Language LLVM Assembly / IR Your Typical Target ISA LLVM Front-end LLVM Back-end LLVM Middle-end

SLIDE 3

Improving Efficiency by Lifting Target

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LLVM

High-Level Programming Language LLVM Assembly / IR Your Typical Target ISA LLVM Front-end LLVM Back-end LLVM Middle-end Imsys ISA for LLVM

SLIDE 4

Agenda

1. Imsys Company and the IoT
2. Imsys Lean Processing Technology
3. Imsys ISA for LLVM

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SLIDE 5

Imsys AB

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Device Module IC IP

SLIDE 6

Networked Embedded Controllers

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SLIDE 7

Imsys EMBLA Single Controller Solution for the IoT

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SLIDE 8

High-Level Software Platform

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Application Code C/C++ Java Executable Binary LLVM Integrated Development Environment

SLIDE 9

Improving Efficiency by Reducing the ISA Gap

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LLVM

High-Level Programming Language LLVM Assembly / IR Your Typical Target ISA LLVM Front-end LLVM Back-end LLVM Middle-end Imsys ISA for LLVM

SLIDE 10

Abstraction Layers

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Imsys Processor Core Imsys Instruction Set Support ISAL ISAJ Application Code JAVA Assembly/C/C++

SLIDE 11

A Forgotten Layer of Abstraction

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Software Hardware

Software Microcode Hardware

SLIDE 12

The Processor Architect’s Best Friend

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IO Microprogram Mult. ALU MEM Ctrl. Addr.

SLIDE 13

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Microcode, what is it good for?

Complete Deterministic Control Flexibility Soft- Reconfigurability Minimal Hardware Maximum Efficiency

SLIDE 14

Abstraction Layers Revisited

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Imsys Processor Core Imsys Instruction Set Support Application Code Software Microcode Hardware ISAL

SLIDE 15

A Unique Balance between Hardware and Software

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Instruction Set Architecture Application

Compiler Microcode

Balanced Rich ISA Domain- specific Operations

Instruction Set Architecture Operation-Oriented Hardware Architecture

SLIDE 16

Improving Efficiency by Matching LLVM Assembly

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LLVM

High-Level Programming Language LLVM Assembly / IR Your Typical Target ISA LLVM Front-end LLVM Back-end LLVM Middle-end Imsys ISA for LLVM

SLIDE 17

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LLVM Assembly ISAL

Semantically matching instructions

LLVM back-end for ISAL

Simple, efficient, general LLVM

Matching LLVM Assembly

LLVM middle-end

Direct use of

ptimizations

SLIDE 18

Meeting a Constrained Reality

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LLVM Assembly ISAL Operations Instructions & intrinsic functions Single Value Types Virtually unlimited Set of integer, floating point, pointer, and vector types Registers Unlimited Register windows Arguments Source and destination registers Registers with support of accumulating in source registers, immediate values Binary Representation Bitcode Custom dense binary coding Additional system operations

SLIDE 19

Optimized Operation Sequences

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a ≔ a + b

pcode

dst src1 src2

Accumulating in source register

pcode

src1 src2

Immediate values

a ≔ a + 42 move b 42 add a a b add.imm a a 42 add.upd.imm a 42 add a a b add.upd a b

SLIDE 20

Optimized Binary Representation

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Intstruction Lengths (Bytes)

7 198 465 258 161 11 1 4

Number of Instructions

1 2 3 4 5 6 7 8 9 10

Variable-length Instructions

Maximize Code Density Optimize Microcode Size Minimize Execution Time

SLIDE 21

0,5 1 1,5 2 2,5 Imsys Cortex-M0+ Cortex-M4 x86 x64 4/2/2018 FOSDEM 2018 LLVM devroom 22

Average Binary Size of TI Suite

ARM Cortex requires 35%+ more, Intel 80%+ more program memory.

SLIDE 22

4/2/2018 FOSDEM 2018 LLVM devroom 23

Dávid Juhász david.juhasz@imsystech.com

ISAL Imsys Processor Core Imsys Firmware

Imsys Lean Processing Technology

LLVM Assembly

LLVM back-end for ISAL

Imsys ISA for LLVM

Leaner is Meaner