Gigabit Ethernet Adapter (GigE) Version 1 Architecture William D. - - PowerPoint PPT Presentation

gigabit ethernet adapter gige version 1 architecture
SMART_READER_LITE
LIVE PREVIEW

Gigabit Ethernet Adapter (GigE) Version 1 Architecture William D. - - PowerPoint PPT Presentation

Gigabit Ethernet Adapter (GigE) Version 1 Architecture William D. Richard, Ph.D. Washington wdr@ee.wustl.edu WASHINGTON UNIVERSITY IN ST LOUIS GigE Design Team William D. Richard Hardware Design Fred Kuhns Protocol Design


slide-1
SLIDE 1

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

wdr@ee.wustl.edu

Gigabit Ethernet Adapter (GigE) Version 1 Architecture

William D. Richard, Ph.D.

slide-2
SLIDE 2

2

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

GigE Design Team

  • William D. Richard

Hardware Design

  • Fred Kuhns

Protocol Design

  • Haoyu Song

FPGA VHDL

  • John D. DeHart

Integration/Test

  • Mike Richards

Board Layout

  • Tom Chaney

Physical Issues

  • John Lockwood

Wrapper/Stuff

  • Jon Turner

Beer?

slide-3
SLIDE 3

3

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

Gigabit Ethernet Adapter (Top)

slide-4
SLIDE 4

4

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

Gigabit Ethernet Adapter (Top)

S/UNI 2XGE

slide-5
SLIDE 5

5

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

Gigabit Ethernet Adapter (Top)

GBIC Guide

slide-6
SLIDE 6

6

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

Gigabit Ethernet Adapter (Top)

125 MHz Osc

slide-7
SLIDE 7

7

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

Gigabit Ethernet Adapter (Top)

62.5 MHz Osc

slide-8
SLIDE 8

8

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

Gigabit Ethernet Adapter (Top)

XC2V1000 FPGA

slide-9
SLIDE 9

9

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

Gigabit Ethernet Adapter (Top)

XC18V04 SPROM

slide-10
SLIDE 10

10

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

Gigabit Ethernet Adapter (Top)

1.5V & 1.8V Regulators

slide-11
SLIDE 11

11

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

Gigabit Ethernet Adapter (Top)

Front Panel

slide-12
SLIDE 12

12

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

Gigabit Ethernet Adapter (Top)

Kludge

slide-13
SLIDE 13

13

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

Gigabit Ethernet Adapter (Bottom)

slide-14
SLIDE 14

14

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

Gigabit Ethernet Adapter (Bottom)

Switch Connector

slide-15
SLIDE 15

15

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

Gigabit Ethernet Architecture

OPP

GBIC

PMC-Sierra S/UNI 2XGE

Gigabit Ethernet Adapter 32 bit

62.5 MHz Clock

FPGA

32 bit 32 bit

IPP

32 bit 2 2 Fiber Twisted Pair

  • r

125 MHz Clock

SPROM

slide-16
SLIDE 16

16

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

GBICs

IBM FIBER GBIC ASANTE’ TWISTED PAIR GBIC

slide-17
SLIDE 17

17

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

GigE With Fiber GBIC

slide-18
SLIDE 18

18

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

GigE With Twisted Pair GBIC

slide-19
SLIDE 19

19

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

Gigabit Ethernet FPGA Architecture

Gigabit Ethernet FPGA

Control Cell Processor ATM-to- Packet/ Packet-to- ATM Wrappers ARP Table ARP Request ARP Reply

S/UNI

IP Forward MAC Frame Parser

SW

32 32 32 32 S/UNI CPU BUS

IP Frame Parser

Update Lookup

VCI=30 VCI=/=30

slide-20
SLIDE 20

20

Washington

WASHINGTON UNIVERSITY IN ST LOUIS

William D. Richard- 6/19/2002 2:29 PM

  • Two copies fabricated initially
  • FPGA switch and MAC loopback tests ok
  • 98 additional copies in process at fab house
  • Software simulation completed and tested
  • FPGA VHDL coding underway
  • Delivery to kits groups expected ____
  • Each kits group should receive ____

GigE Adapter Hardware Status