Gigabit Ethernet Adapter (GigE) Version 1 Architecture William D. - PowerPoint PPT Presentation

Gigabit Ethernet Adapter (GigE) Version 1 Architecture William D. Richard, Ph.D. Washington wdr@ee.wustl.edu WASHINGTON UNIVERSITY IN ST LOUIS

GigE Design Team • William D. Richard Hardware Design • Fred Kuhns Protocol Design • Haoyu Song FPGA VHDL • John D. DeHart Integration/Test • Mike Richards Board Layout • Tom Chaney Physical Issues • John Lockwood Wrapper/Stuff • Jon Turner Beer? Washington William D. Richard- 6/19/2002 2:29 PM 2 WASHINGTON UNIVERSITY IN ST LOUIS

Gigabit Ethernet Adapter (Top) Washington William D. Richard- 6/19/2002 2:29 PM 3 WASHINGTON UNIVERSITY IN ST LOUIS

Gigabit Ethernet Adapter (Top) S/UNI 2XGE Washington William D. Richard- 6/19/2002 2:29 PM 4 WASHINGTON UNIVERSITY IN ST LOUIS

Gigabit Ethernet Adapter (Top) GBIC Guide Washington William D. Richard- 6/19/2002 2:29 PM 5 WASHINGTON UNIVERSITY IN ST LOUIS

Gigabit Ethernet Adapter (Top) 125 MHz Osc Washington William D. Richard- 6/19/2002 2:29 PM 6 WASHINGTON UNIVERSITY IN ST LOUIS

Gigabit Ethernet Adapter (Top) 62.5 MHz Osc Washington William D. Richard- 6/19/2002 2:29 PM 7 WASHINGTON UNIVERSITY IN ST LOUIS

Gigabit Ethernet Adapter (Top) XC2V1000 FPGA Washington William D. Richard- 6/19/2002 2:29 PM 8 WASHINGTON UNIVERSITY IN ST LOUIS

Gigabit Ethernet Adapter (Top) XC18V04 SPROM Washington William D. Richard- 6/19/2002 2:29 PM 9 WASHINGTON UNIVERSITY IN ST LOUIS

Gigabit Ethernet Adapter (Top) 1.5V & 1.8V Regulators Washington William D. Richard- 6/19/2002 2:29 PM 10 WASHINGTON UNIVERSITY IN ST LOUIS

Gigabit Ethernet Adapter (Top) Front Panel Washington William D. Richard- 6/19/2002 2:29 PM 11 WASHINGTON UNIVERSITY IN ST LOUIS

Gigabit Ethernet Adapter (Top) Kludge Washington William D. Richard- 6/19/2002 2:29 PM 12 WASHINGTON UNIVERSITY IN ST LOUIS

Gigabit Ethernet Adapter (Bottom) Washington William D. Richard- 6/19/2002 2:29 PM 13 WASHINGTON UNIVERSITY IN ST LOUIS

Gigabit Ethernet Adapter (Bottom) Switch Connector Washington William D. Richard- 6/19/2002 2:29 PM 14 WASHINGTON UNIVERSITY IN ST LOUIS

Gigabit Ethernet Architecture 62.5 MHz Clock 125 MHz Clock Fiber OPP 32 bit 32 bit 2 PMC-Sierra or GBIC S/UNI FPGA 2XGE 2 32 bit 32 bit Twisted Pair IPP SPROM Gigabit Ethernet Adapter Washington William D. Richard- 6/19/2002 2:29 PM 15 WASHINGTON UNIVERSITY IN ST LOUIS

GBICs IBM FIBER GBIC ASANTE’ TWISTED PAIR GBIC Washington William D. Richard- 6/19/2002 2:29 PM 16 WASHINGTON UNIVERSITY IN ST LOUIS

GigE With Fiber GBIC Washington William D. Richard- 6/19/2002 2:29 PM 17 WASHINGTON UNIVERSITY IN ST LOUIS

GigE With Twisted Pair GBIC Washington William D. Richard- 6/19/2002 2:29 PM 18 WASHINGTON UNIVERSITY IN ST LOUIS

Gigabit Ethernet FPGA Architecture Gigabit Ethernet FPGA IP 32 IP VCI=/=30 32 Frame Forward VCI=30 Parser Lookup ARP Control Table Update ATM-to- Cell Packet/ SW S/UNI Processor ARP Packet-to- Request ATM Wrappers ARP Reply MAC 32 Frame 32 Parser S/UNI CPU BUS Washington William D. Richard- 6/19/2002 2:29 PM 19 WASHINGTON UNIVERSITY IN ST LOUIS

GigE Adapter Hardware Status • Two copies fabricated initially • FPGA switch and MAC loopback tests ok • 98 additional copies in process at fab house • Software simulation completed and tested • FPGA VHDL coding underway • Delivery to kits groups expected ____ • Each kits group should receive ____ Washington William D. Richard- 6/19/2002 2:29 PM 20 WASHINGTON UNIVERSITY IN ST LOUIS