Front-End and ADC ASIC Design Front End and ADC ASIC Design Shaorui - PowerPoint PPT Presentation

Front-End and ADC ASIC Design Front End and ADC ASIC Design Shaorui Li, Gianluigi de Geronimo*, Jack Fried, Wenbin Hou, Neena Shaorui Li, Gianluigi de Geronimo , Jack Fried, Wenbin Hou, Neena Nambia*, Emerson Vernon, Krithika Yethiraj, and Veljko Redeka Instrumentation Division, Brookhaven National Lab

Outline • Introduction of cold front ‐ end (FE) and ADC ASICs for LAr TPC Introduction of cold front end (FE) and ADC ASICs for LAr TPC • CMOS modeling and design for cold electronics • LAr FE ASIC: ‐ Optimizing input MOSFET under power constraint ‐ Crosstalk of Adjacent Channels ‐ Performance of FE ASIC in MicroBooNE Performance of FE ASIC in MicroBooNE • LAr ADC ASIC: ‐ ASIC Feature and operation ‐ Current ‐ mode Domino architecture • CMOS lifetime study for cold electronics ‐ Basics on hot ‐ carrier effects and lifetime B i h t i ff t d lif ti ‐ CMOS lifetime in dc operation: analog front ‐ end ASICs ‐ CMOS lifetime ac operation: logic circuits and FPGAs p g • Further R&D for LAr FE and ADC ASICs 2

• Sense (anode) wires ASIC Specifications from LArTPC: (up to ~ 10m long): ~14-31 kwires/kton dE/dx of 1 MIP: • up to 200 pF/wire 2.1MeV/cm • collecting (Y) • non-collecting (U,V) • charge sensitivity • range ~200 fC • ENC < 1,000 e - • sample/buffer events • ADC 10-12-bit, 1-2 MS/s • digital multiplexing • 128:4 • power constraint • ~ 20 mW /wire (FE+ADc+FPGA) • operation in LAr time First proposed by C. Rubbia, 1977 • > 30 years 3

Cold Electronics voltage regulation (COTS) (< 100mV dropout) front ‐ end ASIC ADC ASIC FPGA (COTS) ~ 5mW/ch. ~ 5mW/ch. ~ 8mW/ch. sensing o e a overall 128:4 8: wires multiplexing 1 x 8 x Parallel work • CMOS lifetime studies front ‐ end cold module serving 128 wires serving 128 wires ~ 2.4 W

Outline • Introduction of Cold Front ‐ End and ADC ASICs for LAr TPC • CMOS modeling and design for cold electronics • LAr FE ASIC: ‐ Noise Sources in Detector Amplifier and ENC Calculation Noise Sources in Detector Amplifier and ENC Calculation ‐ Optimizing input MOSFET under power constraint ‐ Crosstalk of Adjacent Channels ‐ Performance of FE ASIC in MicroBooNE • LAr ADC ASIC: ‐ ASIC Feature and operation ASIC Feature and operation ‐ Current ‐ mode Domino architecture • CMOS lifetime study for cold electronics ‐ Basics on hot ‐ carrier effects and lifetime ‐ CMOS lifetime in dc operation: analog front ‐ end ASICs ‐ CMOS lifetime ac operation: logic circuits and FPGAs CMOS lif ti ti l i i it d FPGA • Further R&D for LAr FE and ADC ASICs 5

CMOS static characteristics vs. T -- I D /V DS & I D /V GS 10 10 MEASURED CMOS018 SIMULATED (foundry parameters) CMOS018 I D vs V DS LN LN RT RT RT RT 8 8 8 6 6 I D [mA] I D [mA] 4 4 4 4 2 2 NMOS, L=0.18µm, W=10µm NMOS, L=0.18µm, W=10µm 0 0 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 0.0 0.3 0.6 0.9 1.2 1.5 1.8 V DS [V] V DS [V] 1 1 10 10 I D vs V GS CMOS018 CMOS018 g m g m 0 0 10 10 I I D I D I ) mV/dec ( ln(10)nV T ) T V -1 -1 n 10 10 [mA], g m [mS] [mA], g m [mS] ) 0 MEASURED 1 SIMULATED ( n LN l (foundry parameters) ( -2 -2 10 10 c e RT LN d / V RT ~72m ~72m m I D I D ~18mV/dec c ~18mV/dec c -3 3 -3 3 10 10 -4 -4 10 10 NMOS, L=0.18µm, W=10µm NMOS, L=0.18µm, W=10µm -5 -5 10 10 0.0 0.0 0.3 0.3 0.6 0.6 0.9 0.9 1.2 1.2 1.5 1.5 1.8 1.8 0.0 0.0 0.3 0.3 0.6 0.6 0.9 0.9 1.2 1.2 1.5 1.5 1.8 1.8 V GS [V] V GS [V] Some differences in saturation voltage, sub-threshold slope, transconductance 6

CMOS static characteristics vs. T -- g m /I D MEASURED 120 NMOS PMOS T=77K 100 L=360nm g m /I D L=270nm L=180nm 80 -1 ] g m /I D [V NMOS PMOS T=300K 60 L=360nm L=270nm 40 40 L=180nm L 180nm 20 CMOS018 0 0 -6 -5 -4 -3 -2 -1 0 1 2 10 10 10 10 10 10 10 10 10 Drain Current Density [mA/mm]   ~ 30 at T 300 K g g q q    Transconductance/ Transconductance/  m m   I nk T ~116 at T 77 K /drain current D B At 77-89K, charge carrier mobility in silicon increases , thermal fl fluctuations decrease with kT/e , resulting in a higher gain , higher g m /I , t ti d ith kT/ lti i hi h i hi h /I higher speed and lower noise . 7

CMOS Noise Spectral Density vs. T T = 300K T = 77K 3 3 10 10 L=180nm, W=1mm (20µm x 50) L=180nm, W=1mm (20µm x 50) ty [nV/  Hz] ity [nV/  Hz] V DS =400mV, T=300K V DS =400mV, T=77K 2 2 10 10 1/f 1/f NMOS NMOS NMOS spectral densi spectral densi I D =3.2mA (IC=3) I D =3.2mA (IC=1) 1 1 10 10 PMOS PMOS I D =0.7mA (IC=1) I D =0.7mA (IC=0.3) fit curve fit curve Input noise Input noise 0 0 10 10 white white   1/f 1/f CMOS018 CMOS018 -1 -1 10 10 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 1.3nV/Hz 1/2 Frequency [Hz] Frequency [Hz] 0.65nV/Hz 1/2 • White noise at 77K is a factor of 2 lower than at 300K • PMOS • 1/f noise amplitude at 77K is a factor of 2 lower than at 300K • NMOS • comparable 1/f noise amplitude at 300 K and 77K • Lorentzian packet at 77K 8

Outline • Introduction of Cold Front ‐ End and ADC ASICs for LAr TPC • CMOS modeling and design for cold electronics • LAr FE ASIC: ‐ Optimizing input MOSFET under power constraint Optimizing input MOSFET under power constraint ‐ Crosstalk of Adjacent Channels ‐ Performance of FE ASIC in MicroBooNE • LAr ADC ASIC: ‐ ASIC Feature and operation ‐ Current ‐ mode Domino architecture Current mode Domino architecture • CMOS lifetime study for cold electronics ‐ Basics on hot ‐ carrier effects and lifetime ‐ CMOS lifetime in dc operation: analog front ‐ end ASICs ‐ CMOS lifetime ac operation: logic circuits and FPGAs • Further R&D for LAr FE and ADC ASICs F th R&D f LA FE d ADC ASIC 9

Analog Front ‐ End ASIC Analog Front ‐ End ASIC Block Diagram digital digital common register BGR, common bias, temp. sensor interface channel register gain & mode & peaking time & bypass mode test coupling mode 5 mode .7 mm analog wire outputs p dual-stage charge amplifier filter ac/dc 16 channels • 16 channels 6.0 mm • charge amplifier, high-order anti-aliasing • band-gap referenced biasing filter • temperature sensor (~ 3mV/ ° C) • programmable gain: 4.7, 7.8, 14, 25 • 136 registers with digital interface mV/fC • 5 5 mW/channel (input MOSFET 3 9 mW) 5.5 mW/channel (input MOSFET 3.9 mW) (charge 55, 100, 180, 300 fC) • single MOSFET test structures programmable filter • ~ 15,000 MOSFETs (peaking time 0.5, 1, 2, 3 µs) • designed for room and cryogenic operation • programmable collection/non-collection • technology CMOS 0 18 µm 1 8 V technology CMOS 0.18 µm, 1.8 V mode (baseline 200, 800 mV) • programmable dc/ac coupling (100µs) 10

Charge Sensor-Transistor Capacitance Mismatch under power constraint      kT  e C C     2   V 2  n d g gs e e 4 4 kT     ENC ENC     Hz n  g 1 2 m p For a very large low noise PMOS transistor W~10mm, L~250nm, W/L~4x10^4, C gs ~10pF. Area in 180 nm process: 160µm x 50µm=8,000µm 2 , equivalent to ~ 10 3 small transistors. The transistor can not match a large (nanofarad) sensor capacitance and we are left with linear dependence of ENC on detector capacitance:    C 1 3 C For low power, CMOS in weak inversion: gsopt gd e C  n det ENC  1 2 p Layout of Input PMOS in LAr FE ASIC 11

ENC vs. Power in the Input Cascode 4000 PMOS 3500 Total ENC L = 270 nm Whit White C DET =200pF 3000 Low-frequency  PK =1  s ons] T = 87 K 2500 rms electro 2000 1500 1500 ENC [r 1000 500 0 3 6 3.6 10m 10m 100m 100m 1 1 10 10 100 100 Power [mW] 12

ENC in LArASIC vs. peaking time of the anti-aliasing filter at 300K and 90K  White series noise 1800 which is dominant T=300K 1600 at short peaking at short peaking T=77K times decreases 1400 C DET =220pF the most with m.s.) 1200 temperature. temperature. (electrons r.m target at 90K 90K 1000  The remaining 800 measured noise is noise is ENC ( 600 600 dominated by 1/f 400 noise, which is simulated whole front-end independent of the independent of the 200 200 s simulated input MOSFET u ated put OS peaking time . 0 0 1 2 3 Peaking Time (µs) 13

Submersion in Liquid Nitrogen (77K) 14 1 4

Crosstalk Study: Basic Feedback Preamplifier Configuration Note: feedback function per se does not affect ENC (feedback components may add noise) ix1 (See slide 20, 21) Preamp input equivalent circuit equivalent circuit DC Gain: R G f 0 Input resistance: Gain ‐ Bandwidth: 1 C   o o R R =>  C in in C g C h f m f Inductance: 1 st pole: Rise time constant:  R => f h C G f f 0 0 1 C   in A periodic R 2  f C C response for h f f 15