Front-End and ADC ASIC Design Front End and ADC ASIC Design Shaorui - - PowerPoint PPT Presentation
Front-End and ADC ASIC Design Front End and ADC ASIC Design Shaorui Li, Gianluigi de Geronimo*, Jack Fried, Wenbin Hou, Neena Shaorui Li, Gianluigi de Geronimo , Jack Fried, Wenbin Hou, Neena Nambia*, Emerson Vernon, Krithika Yethiraj, and
Shaorui Li, Gianluigi de Geronimo*, Jack Fried, Wenbin Hou, Neena Shaorui Li, Gianluigi de Geronimo , Jack Fried, Wenbin Hou, Neena Nambia*, Emerson Vernon, Krithika Yethiraj, and Veljko Redeka Instrumentation Division, Brookhaven National Lab
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(up to ~ 10m long): ~14-31 kwires/kton
dE/dx of 1 MIP: 2.1MeV/cm
(U,V)
1-2 MS/s
(FE+ADc+FPGA)
time
First proposed by C. Rubbia, 1977
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voltage regulation (COTS) (< 100mV dropout)
front‐end ASIC ~ 5mW/ch. FPGA (COTS) ~ 8mW/ch. ADC ASIC ~ 5mW/ch.
sensing
8: multiplexing wires 8 x 1 x front‐end cold module serving 128 wires Parallel work
serving 128 wires ~ 2.4 W
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10 CMOS018 SIMULATED (foundry parameters) LN RT 8 10 CMOS018 MEASURED LN RT
ID vs VDS
4 6 8 RT ID [mA] 4 6 8 RT ID [mA] 2 4 NMOS, L=0.18µm, W=10µm 2 4 NMOS, L=0.18µm, W=10µm 10 10
1
CMOS018 I gm 10 10
1
CMOS018 I gm 0.0 0.3 0.6 0.9 1.2 1.5 1.8 VDS [V] 0.0 0.3 0.6 0.9 1.2 1.5 1.8
VDS [V]
ID vs VGS
3
10
10
c m V / d e c ( l n ( 1 ) n V
T
) MEASURED ID LN RT [mA], gm [mS]
3
10
10
SIMULATED (foundry parameters)
LN
RT ID [mA], gm [mS] c mV/dec (ln(10)nVT) 0.0 0.3 0.6 0.9 1.2 1.5 1.8 10
10
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~18mV/dec ~72m ID NMOS, L=0.18µm, W=10µm 0.0 0.3 0.6 0.9 1.2 1.5 1.8 10
10
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ID NMOS, L=0.18µm, W=10µm ~18mV/dec ~72m 0.0 0.3 0.6 0.9 1.2 1.5 1.8 VGS [V] 0.0 0.3 0.6 0.9 1.2 1.5 1.8 VGS [V]
Some differences in saturation voltage, sub-threshold slope, transconductance
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MEASURED
80 100
NMOS PMOS T=77K L=360nm L=270nm L=180nm
gm/ID
40 60
NMOS PMOS T=300K L=360nm L=270nm L=180nm
gm/ID [V
20 40
L 180nm
CMOS018
~ 30 300
m
at T K g q
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10 10
1
10
2
Drain Current Density [mA/mm]
Transconductance/
~116 77
m D B
g q at T K I nk T At 77-89K, charge carrier mobility in silicon increases, thermal fl t ti d ith kT/ lti i hi h i hi h /I
Transconductance/ /drain current
fluctuations decrease with kT/e, resulting in a higher gain, higher gm /I, higher speed and lower noise.
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10
3
10
3
T = 300K T = 77K
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1/f NMOS L=180nm, W=1mm (20µm x 50) VDS=400mV, T=300K
ty [nV/Hz] 10
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1/f NMOS L=180nm, W=1mm (20µm x 50) VDS=400mV, T=77K
ity [nV/Hz] 10
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NMOS ID=3.2mA (IC=1) PMOS ID=0.7mA (IC=1) fit curve
spectral densi 10
1
ID=3.2mA (IC=3) PMOS ID=0.7mA (IC=0.3) fit curve
spectral densi
1 2 3 4 5 6 7 8
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1/f
white CMOS018
Input noise 10
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1/f
white CMOS018
Input noise
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Frequency [Hz] 10
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Frequency [Hz]
1.3nV/Hz1/2 0.65nV/Hz1/2
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digital
Block Diagram
Analog Front‐End ASIC Analog Front‐End ASIC
common register channel register gain & mode bypass peaking time & mode mode & coupling test BGR, common bias, temp. sensor
digital interface
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mode
wire
analog
.7 mm
dual-stage charge amplifier
filter
ac/dc
16 channels
p
6.0 mm
filter
mV/fC
(charge 55, 100, 180, 300 fC) programmable filter (peaking time 0.5, 1, 2, 3 µs)
5.5 mW/channel (input MOSFET 3.9 mW)
mode (baseline 200, 800 mV)
technology CMOS 0.18 µm, 1.8 V
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Charge Sensor-Transistor Capacitance Mismatch under power constraint
n d gs
2 2
4 V e kT
For a very large low noise PMOS transistor W~10mm,
1 2 g p
4
n m
e kT Hz g
L~250nm, W/L~4x10^4, Cgs~10pF. Area in 180 nm process: 160µm x 50µm=8,000µm2, equivalent to ~ 103 small transistors. The transistor can not match a large (nanofarad) sensor capacitance and we are left with linear dependence of ENC on detector capacitance:
For low power, CMOS in weak inversion:
gsopt gd
det 1 2
n p
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Layout of Input PMOS in LAr FE ASIC
3500 4000
Total ENC Whit PMOS L = 270 nm
2500 3000
White Low-frequency
CDET=200pF
PK=1s
T = 87 K 1500 2000 rms electro
1000
1500 ENC [r 10m 100m 1
3 6
10 100 500 10m 100m 1
3.6
10 100 Power [mW]
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which is dominant at short peaking
1600 1800
T=300K
at short peaking times decreases the most with temperature.
1200 1400
90K m.s.) T=77K CDET=220pF
temperature.
noise is
600 800 1000
target at 90K measured (electrons r.m
noise is dominated by 1/f noise, which is independent of the
200 400 600
simulated input MOSFET simulated whole front-end ENC (
independent of the peaking time.
1 2 3
200
s u ated put OS Peaking Time (µs) 13
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1 4
Note: feedback function per se does not affect ENC (feedback components may add noise)
ix1
Preamp input equivalent circuit
(See slide 20, 21)
f
R G
equivalent circuit 1
R
Gain‐Bandwidth: DC Gain: Input resistance:
Cin
f
C G
f h
R
Inductance:
Rise time constant:
h f m f
R C g C
1st pole:
=> =>
f
1 2
in f h f f
C R C C
A periodic response for
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v (t) Cf C Vo,signal(t) vin(t) R Sense wire Amp Filter Qi(t) Vin,crosstalk(t) Cw Cct (~CW/3‐6) Rin Cf Cw Vo,crosstalk(t) (
W/
) Amp Filter Rin Sense wire
For tp = 1 µs, Cw = 200pF, Rin = 50 Ω Cct crosstalk ratio 30 F 0 225%
ct in
30 pF 0.225% 40 pF 0.3% 50 pF 0.375%
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p
60 pF 0.45% Notice that crosstalk decrease with longer peaking time!
For t = 1 µs C = 200 pF C = 50 pF R = 50 Ω
ct in
For tp = 1 µs, Cw = 200 pF, Cct = 50 pF, Rin = 50 Ω
p
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Courtesy of Sergio Rescia
M1 MP M2 M2xN2 M1xN1 C2 C2xN2 C1 C1xN1 MN
to shaper from input wire dual-stage chargeamplifier
M4 M3
dis en dual-stage charge amplifier
N1 = 20 N2 = 3, 5, 9, 16
C ≈ 180 fF
cal. pulse
CINJ ≈ 180 fF Integrated injection capacitance (10 x 18 µm²) Measured with high-precision external capacitance Integrated pulse generators on ASICs
INJ
Integrated pulse generators on ASICs Charge sensitivity calibration of entire TPC during assembly, cooling and operation
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remained independent of independent of frequency between 1kHz‐1MHz while submerged in liquid g q nitrogen.
O b d t it f i i t FE ASIC i b t 10~20 F On‐board trace capacitance from sensing wire to FE ASIC is about 10~20 pF => ENC contribution: 60~70 electrons
Bandgap Reference:
Signal Measurements: programmable gain, peak time and baseline Signal Measurements: programmable gain, peak time and baseline
K 77 at V 164 . 1 K 300 at V 185 . 1 VBGR
variation ≈ 1.8 %
] non-collecting mode gain [mV/fC]
K 77 at V m 3 . 259 K 300 at mV . 867 VTMP Temperature Sensor:
itude [a.u.] gain [mV/fC] 25 14 7.8 4 7
~ 2.86 mV / °K
Ampl Peak time [µs] 0.5 1.0 2.0 4.7
Programmable gain, peaking time and baseline
2.0 3.0 collecting mode
Maximum charge 55, 100, 180, 300 fC
10 20 30 40 50 Time [µs]
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Mi B NE ld th b d MicroBooNE cold mother board with 12 analog FE ASICs (on top and bottom planes, a total of 192 channels) 50 cold mother boards (8,256 channels) are installed on MicroBooNE TPC
Courtesy of Hucheng Chen 22
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25
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– Sampling rate up to 2 MS/s – Measured resolution 11.7‐bit
O8P/N
ADC16
12 bits 12 bits INP15 INP16 O16P/N
– Low power ADC, ~ 5 mW/ch – Input range 0.2 V to 1.6 V – Clockless operation, ideal for low noise
FIFO
ADC15
/
– Small area favorable for multi‐channel system
ADC1
12 bits INP1 FIFO EMPTY CLK IN
– Low power mode with < 1us wake‐up – Adjustable offset – Multiple options for internal control signals
BIAS ASIC Simplified Block Diagram
0.28mm 27
2.4 mm
Single ADC Layout
ADC Operation & Functional Block
cells reset
4 Phase ADC Conversion
and LSB converted to binary
current
Blocks of ADC
1MSB 64 LSB ll 32 A
ADC Functional Block Diagram
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ADC Design Modules: S&H Circuit ADC Design Modules: S&H Circuit
1) All it h 2 l d 1) All switches 2 closed:
2) A1 charges C1 to VIN
3) M1, M2 current copier multiplier 4) Settling time of S&H 50 ns FIFO integrated on chip for data storage
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Developed in 2007 for small‐angle neutron scattering measurements
Low‐noise front‐end with unity gas‐gain Single‐pad induction (small‐pixel effect) Full size: 196 x 196 pad array (108 n/s) Pad 25 mm², 5 pF, rate 5 kHz / pad
110 l 1 5 W/ h l
300 T = 300K
1.6% on
150 200 250 4µs 2µs 1µs Peaking Time 500ns NC [rms electrons]
neutron peak
1 2 3 4 5 6 7 8 9 10 11 50 100
Dashed Lines: Theoretical Fitting
EN External Input Capacitance [pF]
6.6 x 8.5 mm²
Image from Cd foil, 48x48 pad array 30
External Input Capacitance [pF]
*Australian Nuclear Science and Technology Organization
Phase 1: selects n/63 macro‐currents Ii (32 µA/cell, 150 ns)
1
2
64x500nA Phase 2: on residual current, selects n/64 micro‐currents ii (500 nA/cell, 250 ns)
v1 s1a s1b c1 v2 s2a s2b c2 v64 s64a
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i1 c1 i2 c2 i64
500nA
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Size ~ 4,500 x 6,100 µm²
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dependent dielectric breakdown, and thermal cycling) are strongly temperature Introduction CMOS Lifetime at Cryogenic Temperatures CMOS Lifetime at Cryogenic Temperatures dependent dielectric breakdown, and thermal cycling) are strongly temperature dependent [exp(‐const./kT)] and become negligible at cryogenic temperature.
cryogenic temperature is the degradation (aging) due to channel hot carrier cryogenic temperature is the degradation (aging) due to channel hot carrier effects (HCE).
lif ti h l th NMOS lifetime much longer than NMOS.
degradation in e.g., drain current, transconductance, threshold voltage. The device “fails” if a chosen parameter gets out of the specified circuit design
y g p temperature, is limited by a predictable and a very gradual degradation (aging) mechanism which can be controlled or avoided by device design and operating
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literature, e.g., Hu et al. (1985), and the practices adopted more recently by Chen&Cressler et al. (2006), as well as by industry.
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Basics on Hot Carrier Effects (HCE) ‐1 Basics on Hot Carrier Effects (HCE) ‐1
pair, , resulting in impact ionization. Electrons proceed to the drain. The holes drift to the substrate. The substrate current, (1)
1.3
i
eV
1
i m
q E b d
I C I e
( )
create an interface state (e.g., an acceptor‐like trap), in the Si‐SiO2 interface, , for electrons (~4.6eV for holes). This causes a change in the transistor characteristics (transconductance, threshold, intrinsic
3.7
it
eV
1 sub ds
I C I e
gain). The time required to change any important parameter (the changes in different parameters are correlated) by a specified amount (e.g., gm by ‐ 10%) is defined as the device lifetime. It can be calculated as, (2)
it m
q E
W C e
q = electron charge λ=electron mean free path Em= electric field Id = drain‐source current
dsat ds m
V V E
2 ds
C e I
Ids= drain‐source current W= channel width C1, C2 ‐ constants
l t ff t ( l t i l d ti l) d i b d i i f th i h l l t i fi ld electron effects (electrical and optical) are driven by a common driving force – the maximum channel electric field Em , which occurs at the drain end of the channel.
criterion) by
1.3 ; 3.7 4.2
i it
eV eV
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it i
ds sub ds
1.3 ; 3.7 4.2 2.9 3.2
i it it i
eV eV
Basics of Hot Carrier Effects ‐2 Basics of Hot Carrier Effects ‐2
creation
state creation
the substrate current Isub . Degradation of Vth , Ids and gm is independent of
sub th ds m
temperature if the product λEm≈ λVds is kept constant. Accelerated lifetime test at any temperature (well established by foundries):
transistor is placed under a severe electric field stress (large VDS), to reduce the lifetime due to hot‐electron degradation to a practically observable range, by a drain source voltage considerably higher (~80%) than the nominal voltage
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drain source voltage considerably higher ( 80%) than the nominal voltage.
Stress Test Flow Chart and Layout of test NMOS transistors Stress Test Flow Chart and Layout of test NMOS transistors
2µm Test transistors, NMOS L=180nm, W=10µm (5 fingers x 2µm), designed to have negligible IR drop and power dissipation <15mW in stress tests to prevent p p p temperature change due to self-heating.
Vds=3.2V,77K Vds=2.8V, 77K Vds=3V 77K 100 Vds=3V,77K Vds=2.8V, RT Vds=3V,RT Vds=3.2V,RT 10 ation [%] 10 gm degrada
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10
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1 Stress time [s]
Measurement Type I: “Stress Plot”
it ds
I 1 ln
10
2
10
3
Vds=2.8V
yp
1
ds a sub ds
I W I I
1E7 1E9 1.8V Lifetime ~ 3200 yrs at Vds=1.8V, 77K 1.7V
dsat ds m
V V E q W ln
10
1
10
Vds=2.8V Vds=3.1V Vds=3.0V
/W [s*A/m] 300K Slope ~3.10
10 1000 100000
W (s*A/m)
300K 77K
ASIC design: Vds<1.5V
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Vds=3.0V Vds=3.2V Vds=3.2V *Ids/
77K Slope ~2.94
1E-3 0.1 10
*IDS/W
3.2, 3.1, 3.0, 2.8 V Vds<1.8V
Vds 1.5V
characteristic slope for the
10
10
10 10
Isub/Id
0.1 0.2 0.3 0.4 0.5 0.6 1E-5
1/VDS(V
f p p f interface state generation, , it confirms that the degradation follows basic relations for interface state creation. Substrate current must be measured for this stress plot.
3
it i
a
di f i h i h b
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direct measurements of τ vs. Vds , without measuring the substrate current
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NMOS L=180nm, W=10µm (5x2µm), Vgs=1V
L=270 nm; Vds=1.5V; Ids/W=2.4µA/µm
1E-8
L=270 nm; Vds=1.5V; Ids/W=2.4µA/µm
1E-8 1E-8 10
10
10
10
Stressed lifetime=798s at Vds=3.2V, 77K Stressed lifetime=8506s at Vds=3.2V, 300K Lifetime ~ 5500 yrs at Vds=1.8V, 77K L=360 nm; ‐”‐ ; Ids/W=1.0µA/µm L=9 µm L=270 nm L=9 µm
)
1E-12 1E-11 1E-10 1E-9
L=360 nm; ‐”‐ ; Ids/W=1.0µA/µm L=9 µm L=270 nm L=9 µm
)
1E-12 1E-11 1E-10 1E-9 1E-12 1E-11 1E-10 1E-9 10
10
10
10
Isub/W [A/m] 300K 77K
3 sub
I
Isub/W (A/
m)
1E-16 1E-15 1E-14 1E-13
Isub/W (A/
m)
1E-16 1E-15 1E-14 1E-13 1E-16 1E-15 1E-14 1E-13 1 2 10
10
10
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ASIC design: Vds<1.5V
1E-20 1E-19 1E-18 1E-17 1E-20 1E-19 1E-18 1E-17 1E-20 1E-19 1E-18 1E-17 1/Vds [1/V]
Vds=1.8V
1.5V 1.0V 0.5V
2 4 6 1E 20
1/Vds (1/V) 1.5V 1.0V 0.5V
2 4 6 1E 20 2 4 6 1E 20
1/Vds (1/V)
ds
~5500 years.
LAr TPC (TSMC 180nm, 1.8V node) shows that all transistors are well below
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nominal voltage of 1.8V and at low Isub; Reduced Vds < 1.5 V results in essentially making HCE negligible and a very long extrapolated life time.
5
10
pre stress post stress rt(Hz)]
5
10
t(Hz)] pre stress post stress
Noise Degradation: Less Degradation in PMOS Noise Degradation: Less Degradation in PMOS
NMOS L=180nm, W=10µm (5x2µm) PMOS L=180nm, W=10µm (5x2µm)
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6000 s -> 10% gm degradation input noise [V/sq 10
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nput noise [V/sqrt post stress 12960 s -> 2% gm degradation
300 K 300 K
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Equivalent i Frequency [Hz] 10
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Equivalent in Frequency [Hz] Frequency [Hz] Frequency [Hz] 10
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[V/sqrt(Hz)] pre stress post stress 920 s -> 10% gm degradation post stress 3900 s -> 15% gm degradation 10
10
10
pre stress post stress 1500s stress -> 2% degradation of gm post stress 5000s stress -> 3.5% degradation of gm [V/sqrt(Hz)] 10
10
10
alent Input noise [ 3900 s 5% g deg adat o 10
10
10
6
5000s st ess 3 5% deg adat o
alent input nosie
77 K 77 K
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10 Equiva Frequency [Hz] 10
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Equiva Frequency [Hz]
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PMOS: much less degradation than NMOS
contributor in the front‐end ASIC.
ll th t h l i → id ti l l 1/ V t ti i l V
L 65 nm 130 nm 180 nm ∆Vds/Vds: ~5.3% ~5.7% ~5.5%
all three technologies → identical slope τ vs 1/ Vds at respective nominal Vds
(F lid 6) for τ2/τ1=10 130 nm 65 nm (From slide 6)
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(Data for 130nm and 65nm, courtesy of G. Wu_SMU&FNAL)
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The lifetime is given by,
2
it he it he
Electrons in the MOS channel reach energies well above thermal both at 300K and at 77K . However the mean electron energy, , at the electric field
100
he m
q E meV
2 ds ds
in the range Em ≥100kV/cm. At 77K it is slightly higher, Only a tiny fraction of “hot” electrons reaches the much higher energy required to create an interface state. This makes the exponent in the relation for the lif ti l
he m
q
77 300
he K he K
3.7
it
eV
lifetime very large, Si h i f lif i f li h l diff l f V i
40 4
it it he m
q E E V
Since , the ratio of lifetimes for two slightly different values of Vds is given by,
2 1
it ds
2 1
ds
m ds
E V
2 1 he ds
1 2 ds
Much Longer Lifetime with Longer Device Much Longer Lifetime with Longer Device
the
10%
measured lifetime increased by 1‐2
10%
65 nm
@ 77 K 10% 10%
180 nm 130 nm
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(Data for 130nm and 65nm, courtesy of G. Wu)
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CMOS Lifetime in AC Operation: Logic Circuits and FPGAs CMOS Lifetime in AC Operation: Logic Circuits and FPGAs
b f d i id i h i f h d h f ff i by foundries: considering the ac stress as a series of short dc stresses, each for effective stress time teff during the switching cycle 2tr , strung together.
1/(f t ) compared to dc operation This factor can be quite large at ≤130nm 1/(fck teff ) compared to dc operation. This factor can be quite large at ≤130nm.
teff/tr≈1/4, tr = the gate voltage rise time for NMOS
Quader&Hu et al. (1994)
maximum switching frequency fck ≤1/2tr :
a small fraction of rise/fall time while Vds is high.
ck eff
More detailed estimation can be found in the design manuals of major foundries.
A standard method for evaluating the digital circuit lifetime is to apply accelerated stress test on a Ring Oscillator (RO) and observe the RO frequency degradation under
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stress test on a Ring Oscillator (RO) and observe the RO frequency degradation under severe stress. Degradation of drain current leads to increased rise (propagation) time and reduced frequency.
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Control Logic Experiment Block Diagram Control Logic (locked down in the area with Logic‐ Lock)
A f 30 RO Af h d i i d d Array of 30 ROs. After the device is stressed under one voltage, another array of ROs will be locked down for stress. FPGA Floor Plan
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Freq enc of 30 RO Channels F Hi t f 30 RO Ch l
Frequency of 30 RO Channels Frequency Histogram of 30 RO Channels.
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@400MHz
as . The equation for lifetime projection is modified as: F ll i th b ti lif ti f FPGA t 77K i j t d t b
for 3% degradation criteria, giving a wide margin over the physical target (>20 years) .
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A 2‐year continuous non‐stress test of six regulators biased at different operating condition has b f d Th l f h l i bl h f ll f
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been performed. The output voltage of the regulator is stable over the full range of two years. Voltage drops are due to power glitch (power supply or computer shut down), movement of experiment setup, ect.
Block diagram of TPS74201
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Lifetime Risk Analysis and Amelioration Lifetime Risk Analysis and Amelioration
get out of the region of degradation measurable after 30 years. g g g y
separately from the question of how good the transistor/circuit models for low temperature operation might be The separation of the two issues is easily temperature operation might be. The separation of the two issues is easily accomplished by providing a large lifetime margin, so that the circuit and process margins can be treated independently of aging.
the ASIC data processing speed performance need not suffer due to conservative large lifetime margins.
use in LAr, the lifetime shouldn't represent a concern. The operation and programmability of FPGAs and voltage regulators has been subject of a separate
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study.
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