[PPT] - ASIC Research and Development at Fermilab R. Yarema April 20, 2005 PowerPoint Presentation

SLIDE 1

ASIC Research and Development at Fermilab

R. Yarema

April 20, 2005

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April 20-22, 2005 Super B Factory in Hawaii 2

Main areas

ASIC R&D happening in EED of PPD where we have

capabilities and experience in several diverse areas.

ASIC design at many silicon foundries

– TSMC – IBM – AMS – Agilent – Atmel

ASIC in-house testing

– Wafer level testing – Packaged parts testing

Board level design

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Current Activities

9 ASICs currently in design, fabrication, or under test.

– Readout chip for Resistive Plate Chambers (RPCs) and Gaseous Electron Multipliers (GEMS) – Readout chip for Avalanche Photo Diodes (APDs) – Readout chip for Visible light Photon Counters (VLPCs) – Readout chip for Photomultiplier Tubes (PMTs) – Controller chip for Cockcroft Walton power sources – TDC for straw detectors – Readout chip for pixel detectors – Readout chip for silicon strip detectors – Evaluation chip for 0.13 micron CMOS process

Discuss each device briefly to give over view of design

capabilities - perhaps find new device for your experiment.

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DCAL chip

Digital hadron calorimeter readout chip for

CALICE collaboration

Designed for Fermilab test beam to prove digital

calorimeter concept.

1 m3, 400,000 channel detector
Chip designed to operate with RPCs and GEMs
RPCs used many places (Belle, etc.) GEMs are

relatively new.

Design to be refined for ILC beam structure at a

later time.

Chip is in fabrication (TSMC 0.25 micron CMOS)

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DCAL Specifications

64 channels/chip
1 cm x 1 cm pads
Detector capacitance, 10 to 100 pf
Smallest input signal, 100 fC (RPCs), 5 fC (GEMs)
Largest input signal, 10 pC (RPCs), 100 fC (GEMs)
Chip has adjustable gain for RPCs and GEMs.
Signal pulse width, 3-5 nsec
Trigger less or triggered operation
100 nsec clock cycle
Serial output data – hit pattern

and time stamp

RPC

r

GEM Array DCAL DCAL DCAL 64 Serial Data Output

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April 20-22, 2005 Super B Factory in Hawaii 6 Mask Register Hit Catchers In 0 * * * In 31 In 30 In 29 Mask Register Hit Catchers In 63 * * * In 32 In 33 In 34 TimeStamp (24 bit)

32 bit by 20 stage Pipeline 24 bit by 20 stage Pipeline 32 bit by 20 stage Pipeline

Internal/ External Trigger Control 8 Stage FIFO Steering Logic (a.k.a. Frame Maker) Serializer DataOut ClkOut

32 11 2 Load Done Int Ext Int Ext Ext Int

Tmode Ext TRIG Int TRIGOUT

24 32

Readout Clk Clk Slow Control timeReset Programmable Resets Serial IO

88 Qin Vth Dia Data Mask Mask Dia Data Vth Qin

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DCAL Layout

32 inputs 32 inputs 88 x 20 pipeline

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Avalanche Photo Diode Readout Chip

Chip designed to readout APDs in the proposed NOvA

(Neutrino off axis) experiment at Fermilab.

Design based on previous FNAL chips: SVX4, MASDAX.
Chip is designed for in–spill data taking from Fermilab

neutrino beam and for trigger less operation to search for supernova events and to collect cosmic ray data.

Low noise operation is one of the major problem.
Chip design is complete in TSMC 0.25 micron mixed

signal CMOS

Layout is in progress.

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APD ROC Specifications

32 channels/chip
APD is run at 400 V to give a gain of 100 and provide

signals of 2500 e (min) to the APD readout chip.

Detector capacitance = 10-15 pF
Noise of readout chip = 200 erms max at 10 pF.
First stage: high gain preamplifier with a shaping time of

about 350 nsec.

64 stage switched capacitor array clocked at 500 nsec.
Double correlated samples to reduce noise (various options)
10 bit Wilkinson ADC with linear or pseudo-log ramp
Triggered or trigger less mode
10 bit serial-parallel output data format

32 APDs

Thermoelectric cooler at –15 0C

APD ROC

32 10

Fibers

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10 CK D 10 Shift Register 10 10

GAIN RISE TIME FE RST FE RST

INTEGRATOR SHAPER SAMPLING PIPELINE RING (64 deep) READ AMP ADC COMPARATOR ADC COUNT LATCH 10-BIT GRAY COUNTER

APD READOUT CHIP

IN RAMP GEN. CONTROL LOGIC

Vref

RING CK RAMP CNTL

(One channel of 32 shown)

GRAY CK Write Read CHIP RESET MODE SET

Control Section

Next Chan.

DATA OUT 10

Previous Chan.

Pipeline modes:

1. Triggered

(Write - Stop - Read)

2. Continuous

(no deadtime) Front end reset modes:

1. Switched
2. Continuous

Digitize modes:

1. Cell only (0, 1, ...)
2. DCS (1-0, 2-1, ...)
3. DCS every other

(2-0, 3-1, ...) Ramp modes:

1. Linear
2. Pseudo-log

Ramp Count OUT CK DATA OUT format example: Cell only digitize mode (10-bit DATA words) Data Out, Cell 0 Data Out, Cell 1 Data Out, Cell 63 OUT CK

Ch. 0
Ch. 1
Ch. 2
Ch. 31
Ch. 0
Ch. 1
Ch. 2
Ch. 31
Ch. 0
Ch. 1
Ch. 2
Ch. 31

Digitize Cell 1 Digitize Cell 2 63

Cell 0 1

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TRIP-T

The TRIP-T chip is a multi-channel front-end chip that has a

preamplifier, a fast trigger output, and an analog pipeline for the VLPC based central scintillating fiber tracker and pre- shower detectors at Dzero.

Performs 3 functions

– Detect and send hit information to trigger system every beam crossing. – Store analog signal level in pipeline for readout and digitization later. – Store arrival time of hit within within 100 nsec integration window for readout and digitization later.

The chip is expected to also be used by the proposed Minerva

neutrino experiment.

Chip is designed and layout is finished.
To be submitted about May 15 to TSMC 0.25 micron CMOS

process.

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TRIP-T Specifications

32 channels per chip

– 32 discriminator outputs

Multiplex 32 signals to 16 output lines each clock cycle

– 46 cell deep, analog pipeline; read out after trigger

Pipelined amplitude output to ADC
Pipelined time to voltage converter output to ADC

– To provide 2 nsec resolution

396 nsec clock with 100 nsec signal integration
Chip-wide programmable gain, and discriminator threshold control
Input signal range:

– 4 fC – 150 fC (high gain)

– 1890 fC max (low gain)

Analog ENC: < 1 fC rms.
Detector capacitance: 35 pF

8 VLPCs 8 VLPCs 8 VLPCs 8 VLPCs

TRIP-T

16 1 1 Amplitude Hit time (analog) Discriminator

utputs

Cryostat at 9 0K

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TRIP-T Block diagram

Integrator Variable Gain

Time to Voltage Converter

Disc. Amplitude out V(time) Test 1 of 32 channels Amplitude Pipeline 32 channels x 46 Time Pipeline 32 channels x 46 34 Analog Mux 34 1 1 34 34 32 Digital Mux 16 Discriminator

utput (single

ended CMOS) Amplitude

utput (P. D.)

Timing

utput (P. D.)

Slow control interface Analog Mux 32 Program in Program out Vth Dummy Channel Qin Disc out T-V output Time to Voltage Converter Dummy Channel Pipeline controller

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TRIP-T Chip

Integrators And discriminators Analog Pipeline Programming DACs Slow Control

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QIE9 (Charge Integrator and Encoder)

QIE9 is the latest chip in a series of chips designed for several

experiments: KTEV, CDF, CMS, MINOS, and BTEV. Devices designed for different signal ranges and speed.

Device is used for digitizing signals that cover a wide dynamic

range (16 bits) but need only limited resolution (8 bits).

The QIE9 accepts charge from a PMT, splits the charge with a

current splitter, integrates the charge on 8 binary weighted, parallel ranges, then digitizes the signal from the range of interest and outputs the input charge value as a modified floating point number. Data is processed internally in 3 stage pipeline.

Prototyped in AMS 0.8 micron BiCMOS. Ready for

production. PMT QIE9 3 bit exponent 8 bit mantissa

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QIE 9 Specifications

<0.2% (for .2 pC inputs) Resolution (relative error) < 1 LSB ADC INL << 1 LSB ADC DNL < 5 fC Input noise charge (5 m cable) 50 ohms Input impedance > 20 MHz Analog signal BW 132 ns Gated integration period 300 pC Max input charge 5 fC Least count charge

Typical modified floating-point charge transfer characteristic.

MANTISSA

Q

Q Q Q A (Q )

2

A (Q )

R = 2 R = 1 R = 0

in

(A = Range Scaling Factor)

R = 3 1 2

(R = Range # = Exponent)

Relative error plots for (a) standard and (b) modified floating point.

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QIE9 Block Diagram

R e c e i v e r - S p l it t er

S IG

16/34 Is 8/34 Is 4/34 Is 2/34 Is 8

Is Is

1/34 Is 1/34 Is 1/34 Is 1/34 Is

P h a s e 2 I n t e g r a t e , R a n g e S e l .

Ir Is

8 8

IN T 2 R S T _ C A P 2 R S T _ C O M P 2 E X P 2 S I G 2 R E F2

EXPONENT 16/34 Ir 8/34 Ir 4/34 Ir 2/34 Ir 8

Ir Ir

1/34 Ir 1/34 Ir 1/34 Ir 1/34 Ir

R e c e i v e r - S p l i t t e r

R E F

P h a s e 0 I n t e g r a t e , R a n g e S e l .

Ir Is

8 8

IN T 0 R S T _ C A P 0 R S T _ C O M P 0 E X P 0 S I G 0 R E F0

P h a s e 1 I n t e g r a t e , R a n g e S e l .

Ir Is

8 8

IN T 1 R S T _ C A P 1 R S T _ C O M P 1 E X P 1 S I G 1 R E F1

INT 0- 2 RST_CAP 0-2 RST_COMP 0-2 MUX CONTROL

T IM IN G G E N E R AT O R

CAP_ID

2

3 to 1 D i g i ta l M u x

E X P 0 - 2

3 t o 1 A n a l o g M u x

S I G 0 - 2

3 t o 1 A n a l o g M u x

R E F0 - 2

3 Q IE C lo c k R e se t

MANTISSA

FADC 8 OUTPUT SERIALIZER O u t D a ta C lo c k

Signal input Reference input

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QIE9 Chip

Input Receiver/ splitter Integrators 8 bit ADC Range select

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Resonant Mode Converter Controller (RMCC)

Controller chip for Cockcroft-Walton type of high voltage supply.
Power source for high voltage, low current detectors such as PMTs,

pixel and strip detectors, APDs, etc.

Advantages

– Highly programmable – 12 bit ADC read back – Integrate power near detector – No H. V. connectors – Relatively low cost

Prototype received

– AMI 0.5 micron CMOS

Testing 4 channel board

PMT QIE9 RMCC With HV components HV Control and read back

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Cockcroft Walton Converter using RMCC

+ ref

ref

+ Output polarity VR

+
+

VCO 12 bit ADC Mux Serial data I/O 12 bit DAC Reference +

Temperature

Monitor External input 12 Slow Control Control lines Driver control High Voltage Capacitor and Diode Multiplier Load High voltage resistor divider L C Error Amplifier

RMCC

Bandgap reference

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RMCC

Serial I/O 12 bit DAC 12 bit ADC High current Output drivers Amplifiers

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Multi-channel TDC

Intended for use with straw detectors
TDC features:

– Radiation tolerant (TSMC 0.25 micron CMOS) – 48 channels – Serial CMOS output

To be tailored for application

– 1.65 nsec resolution – Min. input PW = 10 nsec – On chip DAC reference for ASDQ chip

Chip under test

– Appears functional

8ch ASDQ 8ch ASDQ 8ch ASDQ 8ch ASDQ 8ch ASDQ 8ch ASDQ 48 Straw Wires 48 Channel TDC Ref 24 24 1

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Multi-channel TDC Block Diagram

TDC Core Counter Channel 1 Channel 2 Channel 48 Start TDC 48 Inputs Shift Register (Ch 1-48) (Output to be tailored to application) Clk 1 X80 clock multiplier Phase Lock Loop Lock detector 132 nsec reference clock 1.65 nsec clock 1 Serial

utput

Parallel output for channel 1 only 8 Bandgap reference DAC input 8 8 bit DAC To ASDQs 1 1 384

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TDC Chip

48 TDC channels Output Shift Register Phase lock loop 8 bit DAC

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FPIX2

Pixel readout chip designed for the proposed

BTEV experiment.

May be used in Phenix upgrade at BNL
Other applications being considered
Design work complete

– Final production version to be submitted about May 15

16896 pixel detector 6 FIX2 chips bump bonded to detector I/O to FPIX chips

FPIX2 FPIX2 FPIX2 FPIX2 FPIX2 FPIX2

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FPIX2 Specifications

Pixel chip intended for use in Level 1 trigger (a first in HEP)

– All hit information must be read out in 132 nsec – Zero suppressed data readout – 840 Mbit/sec readout capability (1-6 programmable serial outputs)

3 bit ADC in every pixel cell
Low noise with detector (110 e rms)
Low threshold dispersion with detector (250 e rms)

– No individual pixel trim DACs

Intended for 132 nsec beam interaction rate (can be run faster)
50 x 400 micron cells arranged in 22 columns by 128 rows
Tolerates large leakage current (100 nA)
Functionality is highly programmable

– All adjustable parameters set to default values upon startup

Radiation hard to > 30 Mrads.

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FPIX2 Block Diagram

Pixel Unit Cells (22 columns of 128 rows each) End-of-Column logic (22 copies) Core Logic

Core

DAC’s Programmable Registers

Programming Interface

Steering Logic Word Serializer Next Word Block Clock Control Logic Input/Output High Speed Output MCA/MCB (Readout Clock) BCO Clock

Data Output Interface

Only bias voltages required are 2.5V & ground. All I/O is LVDS.

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FPIX2 Layout

Debugging Outputs (to be removed) 128x22 Pixel array End-of-Column Logic Data Output Interface Program Interface Registers and DAC’s LVDS Drivers and I/O pads Internal bond pads for Chip ID

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Pixel Unit Cell

Vff Test Sensor Inject Vref

+

Vdda

Amplifier

Vth0 Vth1 Vth2 Vth7

3 bit FADC

Hit

Binary Encoder Command Interpreter 4 pairs of lines, 3 commands each: Wait for Data Idle Output Data Token & Bus Controller

Pulse ht: [0:2] Row # [0:7] Token In Token Out

Column Bus

Kill Vfb2 Ifb

Bias voltages & currents are set by DAC’s. Fast Hit OR

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Layout of 4 pixels cells (50 µ x 400µ)

12 µm bump pads

Preamp 2nd stage +disc ADC Kill/ inject ADC encoder Digital interface

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FSSR (Fermilab Silicon Strip Readout)

Designed in collaboration with INFN personnel
Originally planned for BTEV experiment
Major requirements

– Same programming interface and data output interface same as FPIX2 – Data driven architecture – no trigger – Programmable shaping times (65-125 nsec) for 132, 264, or 396 nsec BCO – 128 channels/chip – ENC < 1000 erms @ Cdet=20 pF

Measured 220 e + 26 e/pF

– Threshold dispersion < 500 erms

Measured 440 e rms

– Programmable gain of 10 or 6.7mV/fC – 3 bit ADC/channel – Power < 4mw/channel – Detector inputs on 50 u pitch – Radiation hard (TSMC 0.25 µ CMOS)

Pre-production parts received and under test

15 cm Wire bonds Silicon Strip detector Silicon Strip detector

FSSR FSSR FSSR FSSR

Data I/O

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FSSR Block diagram

FSSR Core

– 128 analog channels – 16 sets of logic, each handling 8 channels – Core logic with BCO counter

Programming Interface (slow

control – same as FPIX2 – Programmable registers – DACs

Data Output Interface

– Communicates with core logic – Formats data output – Same as BTEV FPIX chip

Allows common DAQ

128 channels of analog circuits 16 sets of logic each handling 8 analog channels Core Logic To silicon strip detectors Programming Interface DACs Programmable Registers Steering Logic Word Serializer Clock Control Logic Next Block Word Core Data Output Interface BCO clock I/O Readout clock High Speed Output BCO ctr 1 16

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FSSR Channel Electronics

Vth0 Vth1 Vth2 Vth7

3 bit FADC

Hit

Binary Encoder Command Interpreter 4 pairs of lines, 3 commands each: Wait for Data Idle Output Data Token & Bus Controller

Pulse ht: [0:2] Row # [0:7] Token In Token Out

Column Bus

Kill

Fast Hit OR

Gm Cinj Test input CR-(RC)2 Base Line restorer On/off Programmable shaping

Same as FPIX

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FSSR Chip

128 input Bond pads Amplifier- Shaper- BLR End of column logic Program interface DACs ADCs Data Output Interface

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IBM 0.13 micron Evaluation Chip

First venture into 0.13 micron design
Chip includes

– Pixel design based on FPIX2 – Various registers to study SEU – Frequency multiplier (PPL) – Test devices

Initial tests suggest good correlation between simulations

and actual devices.

Interest for possible MAPS applications

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Chip Testing at FNAL

Production testing group for all chips developed at FNAL.

– Wafer level testing

Semiautomatic 8 inch wafer probe station

– Packaged parts testing

Two robotic packaged parts testers
Testing also done for other customers

– CMS ( pixel readout chips, token bit manager chip) – University of Michigan MASDAX chips

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Robotic ASIC Tester

Custom interface board for DUT Robot loaded with 700 chips Pick and place head ASIC tester box * Analog and digital I/O * Serial link to computer Good Bad

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Wafer Testing on Probe Station

Hardware has tested many ASICs.
Probe station

–Semi-automatic –Micro chamber –8” chuck

Data acquisition

–Tester box –Interface PCBs –Computer –Test & measurement equipment

Wafer maps showing Good and bad chips (green shading shows grading)

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Summary

Fermilab ASIC designers have designed chips for numerous

different experiments. – CDF, Dzero, CMS, KTEV, MINOS, NOvA, CALICE, BTEV, etc.

Designs are generally mixed signal with an emphasis on the

analog design.

New areas of current interest include ILC (vertex, tracking,

calorimetry), SNAP (CCD control), PHENIX (mini strips), SCMS (pixels, mini strips).

Always interested in new projects.
For more information, checkout our web page

http://www-ppd.fnal.gov/EEDOfficew/ASIC_Development/asicmain.html.