Evolving ASIC Methodology to Adapt to Technology and EDA Tool Advances Tom Russell Manager ASIC Front-End Methodology IBM Microelectronics
Agenda Technology Advances Emerging Challenges Design Tool Advances ASIC Design Methodology Implications Conclusion
Semiconductor Growth Drivers Transistors / WW S/C Revenue ($B) All businesses, people, objects chip 10000 Network computing Wide area / bandwidth 100B Graphical, voice, multimedia, etc. 10B Many vendors / platforms 1000 Networks Networks 1B PCs / PCs / Internet Internet Servers Servers 100M 100 10M Businesses & some people Mainframes Mainframes Client-server computing Local area connection 1M Text/graphical interface Many vendors / few architectures 10 PCs PCs 100K Businesses 10K Host-based computing Mainframe 1 1K Dumb terminal Today Today 2015 1975 1995 Few vendors / architecture Year
Technology Drivers Cost Phones, PDA's, Smart Phones, PDA's, Smart High Frequency Clothes... Clothes... Bandwidth Memory Power Time to Market Routers, Routers, Hubs, Hubs, Personal Computers Switches... Switches... Computers, Net Computers, Net Storage Storage
Technology Leadership Packaging Interconnects Packaging Interconnects Device Technology Device Technology Chip on Chip, Bulk & SOI CMOS SiGe Solder BiCMOS < 50 nm gates Bumps, MCM >200ghz (polymer Copper & Ceramic) Lithography Lithography Memory Construction Material Changes Memory Construction Material Changes .05um eDRAM SOI 193nm Low K Copper BEOL Deep UV, eBeam CMP 1 Billion Bit Chip, STI DUV '80's eDRAM Litho Sidewall '80's '90's 2000's
Require new materials to continue the pace of performance gains 10 Relative Silicon Capability Growth Breakthrough Breakthrough Technology Technology (Copper, SOI) (Copper, SOI) Conventional CMOS Conventional CMOS Saturates Saturates Bulk 1 1995 2000 2005 2010 2015 Year
Technology Generation Every 18 - 24 Months 0.22µm 7S 7S 1.8V 7S - SOI 7S - SOI 0.18µm 8S/7SF 8S/7SF 8SE 8SE 1.5V 8S2 8S2 Vdd 8S3 8S3 Low-K ILD Increasing 9S 8SF 9S 8SF 0.13µm 1.2V Performance 9S2 9S2 0.1µm 10S 10S 9SF 9SF 1.0V 10S2 10S2 BULK Si SOI 0.07µm 11S 10SF 11S 10SF < 1.0V 1998 1999 2000 2001 2002 2003 2004 2005 Start of Volume Production (T2)
Agenda Technology Advances Emerging Challenges Design Tool Advances ASIC Design Methodology Implications Conclusion
Low-Power Systems Various sleep modes - clock gating - disabling µP µP sub-elements - disable entire µP memory memory Tradeoff power and performance custom custom logic logic - Control parasitics for lowest leakage Multi-voltage operation - Circuit design for low voltage, - "power down" non critical circuits data retention state - "power-off" circuits while retaining - Higher voltage operation for state read/write
Low-Power Systems * Power Tradeoffs Best Made during Architectural Design Phase - System Issue - Performance, Power, Area - Requires functional understanding of design - More leverage than late analysis and fix-up - Faster tradeoff iteration at higher abstraction . . . but must have access to technology feature set (multi-threshold libraries, voltage islands etc.) * Early Power Analysis Requires Improved Modeling Accuracy - Technology-specific models for timing accuracy - Ability to evaluate multiple operating conditions quickly *Solution involves technology, education, tools, and methodology
Signal Integrity and Noise Coupled Noise - "Aggressor" nets couple signals into "victim" nets - Coupling primarily due to line-to-line capacitance - Example shows three aggressors and one victim (A-V-A) - Many other configurations possible over multiple metal levels
Signal Integrity and Noise * Noise is a progressively worsening problem as geometries shrink * Could become a gate to customer "first time right" success * Noise is a complex, multifaceted problem - Statistical phenomenon - Several types: coupled, supply, substrate - Layered approach required to address each type *Solution involves education, design, tools, and methodology * Objective is to reduce the probability of a design failure while minimizing impact to design TAT, performance, and density
Signal Integrity and Noise * Noise is not a new problem - faced by I/O designers for 20+ years * May cause false switching or timing fails * Evolved / evolving into an on-chip problem * Aggravated by many issues: - Faster chips -> higher edge rates, less Dt tolerance - Higher edge rates -> more coupled and supply noise - Lower Vdd -> lower noise immunity - Wire scaling -> more R, more capacitive coupling (Ccoupled/Ctotal) - Constant power @ lower Vdd -> more I -> more I-R loss - Higher I/O Vdd supplies -> increased coupled noise - Increasing substrate currents -> more substrate noise
Signal Integrity and Noise * Noise is a statistical phenomenon Statistical problems can be significantly reduced but not fully eliminated * Noise reduction can be costly if done without finesse Design TAT, performance and density impacts - "How can I fix 40,000 failing nets?" - "Why did my critical path slow down by 40%?" * Noise avoidance as important as noise analysis - Limit size of remaining problem to analyze - Limit number of nets to repair Noise avoidance via education, design, tools, and methodology
Agenda Technology Advances Emerging Challenges Design Tool Advances ASIC Design Methodology Implications Conclusion
ASIC Design Tool Evolution RTL IP Design Design Design RTL IP Logic Planning Design Design Synthesis Floorplanning Synthesis, Place and Route DFT, Clocks Optimization DFT, Clocks Placement & Optimization Integration, ATPG & Release Routing Integration, ATPG & Release Manufacturing Manufacturing
Agenda Technology Advances Emerging Challenges Design Tool Advances ASIC Design Methodology Implications Conclusion
Design Methodology Must Evolve To Enable Access to Technology Features To Enable Access to Technology Features Early, Architectural-Stage Vision is Essential Modeling must be evermore accurate in predicting ultimate results Tool execution must be fast to enable iteration Issues resolved early yield enormous TAT benefits To Efficiently Employ New-Generation Design Tools To Efficiently Employ New-Generation Design Tools Integrated Synthesis, Placement Dictates "Same Seat" execution of synthesis and placement steps Sign-off point must move to accommodate Advent of Design Planning Tools Enables Early Focus on Technology Features Performance, Power, Area, Testability, Cost, Signal Integrity Key to Accelerating ASIC Turn-around-time
New Design Methodology: Two Engagement Models Customer Supplier Synthesis DFT & Clocks RTL Design Final Place & & Verification Integrate, Floorplanning Route ATPG, and Release Placement Optimizations Traditional Flow Analysis Late Sign-off Customer Supplier Synthesis & RTL Design Final Route Placement Integrate, & Verification Planning and Optimizations ATPG, Optimizations Release RTL Planning DFT & Clocks Design Planning Flow Supplier Customer Early Sign-off
New Design Methodology: Efficient and Precise 3. Preliminary Netlist Feedback 1. Analysis Netlist Feedback 4. Final Design Synthesis Synthesis DFT & Clocks DFT & Clocks Complete RTL Design RTL Design Final Place & Final Place & & Verification & Verification Integrate, Floorplanning Floorplanning Route Route ATPG, Traditional Flow and Traditional Flow and Release Placement Placement Optimizations Optimizations Analysis Analysis 2. Floorplan Netlist Feedback 1. Technology Usage Feedback Synthesis & Synthesis & 2. Final RTL Design RTL Design Final Final Design Route Route Placement Placement Complete Integrate, & Verification & Verification Planning Planning and and Optimizations Optimizations ATPG, Optimizations Optimizations Release RTL Planning RTL Planning DFT & Clocks DFT & Clocks Design Planning Flow Design Planning Flow
Modeling Dependencies of the New Methodology Model Accuracy is More Important than Ever For Early Design Planning: Models must enable fast tradeoff experimentation Must provide visibility into power, timing, area vs. environment, process Models must enable accurate prediction of downstream results High-Level Abstraction path Required accuracy with optimal runtime For Detailed Design: Model accuracy must approach 100% precision to overcome pessimism Accuracy guaranteed by silicon supplier
Agenda Technology Advances Emerging Challenges Design Tool Advances ASIC Design Methodology Implications Conclusion
ASIC Methodology 2002 ASIC Methodology is Evolving to Support Technology and Tool Advances ASIC Methodology is Evolving to Support Technology and Tool Advances Signoff Model moving In "both directions" Signoff Model moving In "both directions" Early Signoff ASIC Supplier Handles Silicon Details Customer Focus on Function Late Signoff Customer Owns Both Function and Silicon Implementation There will be ASIC Customers for Both Engagement Models There will be ASIC Customers for Both Engagement Models
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