Evolving ASIC Methodology to Adapt to Technology and EDA Tool - - PowerPoint PPT Presentation

Evolving ASIC Methodology to Adapt to Technology and EDA Tool Advances

Tom Russell Manager ASIC Front-End Methodology IBM Microelectronics

Agenda Technology Advances Emerging Challenges Design Tool Advances ASIC Design Methodology Implications Conclusion

1975 1995 2015 Year

1 10 100 1000 10000 WW S/C Revenue ($B)

Semiconductor Growth Drivers

Businesses Host-based computing Mainframe Dumb terminal Few vendors / architecture

Mainframes Mainframes

1B 1M 10M 100M 10B 100K 10K 1K 100B

PCs PCs

PCs / PCs / Servers Servers

Businesses & some people Client-server computing Local area connection Text/graphical interface Many vendors / few architectures

Today Today

All businesses, people, objects Network computing Wide area / bandwidth Graphical, voice, multimedia, etc. Many vendors / platforms

Networks Networks

Internet Internet

Transistors / chip

Technology Drivers

Cost High Frequency Bandwidth Memory Power Time to Market

Phones, PDA's, Smart Phones, PDA's, Smart Clothes... Clothes... Routers, Routers, Hubs, Hubs, Switches... Switches... Computers, Net Computers, Net Storage Storage

Personal Computers

Technology Leadership

Device Technology Device Technology Interconnects Interconnects Lithography Lithography

Bulk & SOI CMOS < 50 nm gates SiGe BiCMOS >200ghz

Memory Memory

1 Billion Bit Chip, eDRAM

Packaging Packaging

Chip on Chip, Solder Bumps, MCM (polymer & Ceramic) Deep UV, eBeam Copper

'80's

Construction Material Changes Construction Material Changes

'80's '90's 2000's Sidewall Copper BEOL DUV Litho STI CMP SOI 193nm eDRAM .05um Low K

Require new materials to continue the pace of performance gains

1995 2000 2005 2010 2015

Year

1 10

Relative Silicon Capability Growth

Bulk

Breakthrough Breakthrough Technology Technology (Copper, SOI) (Copper, SOI) Conventional CMOS Conventional CMOS Saturates Saturates

Technology Generation Every 18 - 24 Months

Start of Volume Production (T2)

BULK Si

1.8V 1.2V < 1.0V 1.0V

Low-K ILD

Vdd

1998 1999 2000 2001 2002 2003 2004 2005

1.5V

7S 7S 7S - SOI 7S - SOI

0.22µm 0.18µm 0.13µm 0.07µm 0.1µm

Increasing Performance

8S/7SF 8S/7SF 8S2 8S2 8S3 8S3 8SE 8SE 8SF 8SF 9S2 9S2 10S 10S 10S2 10S2 11S 11S SOI 9S 9S 9SF 9SF 10SF 10SF

Agenda Technology Advances Emerging Challenges Design Tool Advances ASIC Design Methodology Implications Conclusion

Low-Power Systems

µP µP memory memory custom custom logic logic

Various sleep modes

• clock gating
• disabling

sub-elements

• disable entire µP

Tradeoff power and performance Multi-voltage operation

• "power down" non critical circuits
• "power-off" circuits while retaining

state

• Control parasitics for lowest leakage
• Circuit design for low voltage,

data retention state

• Higher voltage operation for

read/write

Low-Power Systems

* Power Tradeoffs Best Made during Architectural Design Phase

• System Issue - Performance, Power, Area
• Requires functional understanding of design
• More leverage than late analysis and fix-up
• Faster tradeoff iteration at higher abstraction

. . . but must have access to technology feature set (multi-threshold libraries, voltage islands etc.) * Early Power Analysis Requires Improved Modeling Accuracy

• Technology-specific models for timing accuracy
• Ability to evaluate multiple operating conditions quickly

*Solution involves technology, education, tools, and methodology

Signal Integrity and Noise

Coupled Noise

• "Aggressor" nets couple signals into "victim" nets
• Coupling primarily due to line-to-line capacitance
• Example shows three aggressors and one victim (A-V-A)
• Many other configurations possible over multiple metal levels

Signal Integrity and Noise

* Noise is a progressively worsening problem as geometries shrink * Could become a gate to customer "first time right" success * Noise is a complex, multifaceted problem

• Statistical phenomenon
• Several types: coupled, supply, substrate
• Layered approach required to address each type

*Solution involves education, design, tools, and methodology * Objective is to reduce the probability of a design failure while minimizing impact to design TAT, performance, and density

Signal Integrity and Noise

* Noise is not a new problem - faced by I/O designers for 20+ years * May cause false switching or timing fails * Evolved / evolving into an on-chip problem * Aggravated by many issues:

• Faster chips -> higher edge rates, less Dt tolerance
• Higher edge rates -> more coupled and supply noise
• Lower Vdd -> lower noise immunity
• Wire scaling -> more R, more capacitive coupling (Ccoupled/Ctotal)
• Constant power @ lower Vdd -> more I -> more I-R loss
• Higher I/O Vdd supplies -> increased coupled noise
• Increasing substrate currents -> more substrate noise

Signal Integrity and Noise

* Noise is a statistical phenomenon Statistical problems can be significantly reduced but not fully eliminated * Noise reduction can be costly if done without finesse Design TAT, performance and density impacts

• "How can I fix 40,000 failing nets?"
• "Why did my critical path slow down by 40%?"

* Noise avoidance as important as noise analysis

• Limit size of remaining problem to analyze
• Limit number of nets to repair

Noise avoidance via education, design, tools, and methodology

Agenda Technology Advances Emerging Challenges Design Tool Advances ASIC Design Methodology Implications Conclusion

ASIC Design Tool Evolution

Design Planning RTL Design IP Design Synthesis, Place and Route Optimization DFT, Clocks

Integration, ATPG & Release

Manufacturing RTL Design Logic Synthesis Floorplanning DFT, Clocks Routing Placement & Optimization Manufacturing

Integration, ATPG & Release

IP Design

Agenda Technology Advances Emerging Challenges Design Tool Advances ASIC Design Methodology Implications Conclusion

Design Methodology Must Evolve

To Enable Access to Technology Features To Enable Access to Technology Features Early, Architectural-Stage Vision is Essential Modeling must be evermore accurate in predicting ultimate results Tool execution must be fast to enable iteration Issues resolved early yield enormous TAT benefits

To Efficiently Employ New-Generation Design Tools To Efficiently Employ New-Generation Design Tools

Integrated Synthesis, Placement Dictates "Same Seat" execution of synthesis and placement steps Sign-off point must move to accommodate Advent of Design Planning Tools Enables Early Focus on Technology Features Performance, Power, Area, Testability, Cost, Signal Integrity Key to Accelerating ASIC Turn-around-time

RTL Design & Verification Synthesis Floorplanning Placement Analysis DFT & Clocks Final Place & Route and Optimizations

Traditional Flow

Integrate, ATPG, Release

RTL Design & Verification RTL Planning

Final Planning

Synthesis & Placement Optimizations DFT & Clocks Route and Optimizations

Design Planning Flow

Integrate, ATPG, Release

Customer Supplier Late Sign-off Customer Supplier Early Sign-off Customer Supplier

New Design Methodology: Two Engagement Models

New Design Methodology: Efficient and Precise

• 1. Analysis Netlist Feedback
• 2. Floorplan Netlist Feedback
• 3. Preliminary Netlist Feedback

RTL Design RTL Design & Verification & Verification Synthesis Synthesis Floorplanning Floorplanning Placement Placement Analysis Analysis DFT & Clocks DFT & Clocks Final Place & Final Place & Route Route and and Optimizations Optimizations

Traditional Flow Traditional Flow

• 4. Final

Design Complete

Integrate, ATPG, Release

RTL Design RTL Design & Verification & Verification RTL Planning RTL Planning

Final Final Planning Planning

Synthesis & Synthesis & Placement Placement Optimizations Optimizations DFT & Clocks DFT & Clocks Route Route and and Optimizations Optimizations

Design Planning Flow Design Planning Flow

• 2. Final

Design Complete Integrate,

ATPG, Release

• 1. Technology Usage Feedback

Model Accuracy is More Important than Ever For Early Design Planning: Models must enable fast tradeoff experimentation Must provide visibility into power, timing, area vs. environment, process Models must enable accurate prediction of downstream results High-Level Abstraction path Required accuracy with optimal runtime For Detailed Design: Model accuracy must approach 100% precision to overcome pessimism Accuracy guaranteed by silicon supplier

Modeling Dependencies of the New Methodology

Agenda Technology Advances Emerging Challenges Design Tool Advances ASIC Design Methodology Implications Conclusion

ASIC Methodology 2002

ASIC Methodology is Evolving to Support Technology and Tool Advances ASIC Methodology is Evolving to Support Technology and Tool Advances Signoff Model moving In "both directions" Signoff Model moving In "both directions" Early Signoff ASIC Supplier Handles Silicon Details Customer Focus on Function Late Signoff Customer Owns Both Function and Silicon Implementation

There will be ASIC Customers for Both Engagement Models There will be ASIC Customers for Both Engagement Models