EDA Challenges in Systems EDA Challenges in Systems EDA Challenges - - PowerPoint PPT Presentation

EDA Challenges in Systems EDA Challenges in Systems EDA Challenges in Systems EDA Challenges in Systems Integration Integration

• J. A. G. Jess

NSF EDA Workshop July 8 and 9 2009 July 8 and 9, 2009

Why should IC Why should IC-

• EDA and

EDA and Electronics Systems Electronics Systems Manufacturers move closer? Manufacturers move closer? Manufacturers move closer? Manufacturers move closer?

 With Moore’s Law electronic systems move

b C’ ff hi i i to become IC’s – off-chip communication moves on-chip facing IC designers with i i l systems communication legacy

 Electronics Systems market is roughly six

times the market of IC’s – interesting for EDA to have the ESM’s as customers

Two Paradigms: Two Paradigms: Two Paradigms: Two Paradigms: Heterogeneous Heterogeneous -

• Homogeneous

Homogeneous

heterogeneous homogeneous heterogeneous homogeneous Many specialized (optimized) Computing A few (at times frequently replicated) general compute compute engine types Computing replicated) general compute engine types (X86 API,…) M i li d A few universally used Many specialized “communication fabrics” Communi- cation A few universally used standard bus protocols (PCIe, AMBA AXI,…) Many different memory types, designer in control

• f memory policy

Memory Standard (virtual) Random Access Memory supported by caches

Attempt of Attempt of a a Taxonomy Taxonomy

Heterogeneous Homogeneous

Good Compute Performance Compute Performance to

to Power Ratio (MOPs/Wsec)

Small “Bill of Material”

(BoM e g area) Power Ratio medium (improving!) but unpredictable

BoM medium to large

(BoM, e.g. area)

BoM medium to large Lack of Flexibility Large NRE cost, limited re- Very flexible through

programming on “Virtual a ge N cost, ted e use Machine”

Extensive re-use of SW and

HW HW

Sample Hardware Sample Hardware Architecture Mobile Device Architecture Mobile Device (~2005) (~2005) ( 2005) ( 2005)

RF/IF Display 2Mp Camera RF/IF Display Baseband DSP & ARM Applications

• Proc. ARM

Module NAND Card Card Mobile SDRAM 128/256 Mb NAND Flash 256 Mb Cellular RAM 16 Mb Burst NOR 32 Mb 128/256 Mb 256 Mb 16 Mb 32 Mb

Devices sharing Interconnect Devices sharing Interconnect

RF/IF Display Speaker Mik Communication (“Bus”) Interface xMp RF/IF Mike

ge

CPU DSP Core CPU DSP Core xMp Camera Module CPU DSP Core NAND Burst O Mobile SDRAM NAND Fl h Cellular

bridg More Functions More Peripherals

NAND Card NOR 32 Mb SDRAM 128/256 Mb Flash 256 Mb RAM 16 Mb

Peripherals

Heterogenity vs. Homogenity Heterogenity vs. Homogenity

Processor Arch. Homogenious Processor Arch. ect Arch. ect Arch. ct Arch. Interconne Interconne Interconnec Processor Arch. Heterogenious I

Basic Challenges Basic Challenges

 How to assign performance metrics to the

co-ordinates of the cube?

 Given those metrics, how to establish tools

providing decision support for designers providing decision support for designers (and roadmap makers)?

“Systems Integration” “Systems Integration”

 A large portion of the design effort is concerned  A large portion of the design effort is concerned

with matching the on-chip and inter-chip communication- and memory performance with h ifi i the specifications

 Communication is critical for Timing and Power  H

d l ith t ti h d i t t?

 How deal with contention on shared interconnect?  Stability of system modes and mode-transitions?  Verification is hampered by the lack of formal  Verification is hampered by the lack of formal

design documentation on system level

 Up to now there seems to be little tooling support

Up to now there seems to be little tooling support – lots of manual code development & guessing

Thank you!