ECE 5745 Complex Digital ASIC Design Section 1: ASIC Flow Front-End - PowerPoint PPT Presentation

ECE 5745 Complex Digital ASIC Design Section 1: ASIC Flow Front-End Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5745

Multi-Level Modeling Methodologies Functional-Level Modeling Applications – Behavior Algorithms Cycle-Level Modeling Compilers – Behavior – Cycle-Approximate Instruction Set Architecture – Analytical Area, Energy, Timing Microarchitecture Register-Transfer-Level Modeling VLSI – Behavior – Cycle-Accurate Timing – Gate-Level Area, Energy, Timing Transistors 2 / 10

Multi-Level Modeling Methodologies Functional-Level Modeling Multi-Level Modeling Challenge – Algorithm/ISA Development FL, CL, RTL modeling – MATLAB/Python, C++ ISA Sim use very different Cycle-Level Modeling languages, patterns, – Design-Space Exploration tools, and methodologies – C++ Simulation Framework – SW-Focused Object-Oriented SystemC is a good example of a unified multi-level – gem5, SESC, McPAT modeling framework Register-Transfer-Level Modeling Is SystemC the best – Prototyping & AET Validation we can do in terms of – Verilog, VHDL Languages productive – HW-Focused Concurrent Structural multi-level modeling? – EDA Toolflow 2 / 10

VLSI Design Methodologies HDL HPF HGF Hardware Description Hardware Preprocessing Hardware Generation Language Framework Framework HDL Mixed HDL Host Language HDL (Verilog) (Verilog+Perl) (Verilog) (Verilog) (Scala) synth synth gen synth gen DUT DUT DUT' DUT DUT' Sim Sim Sim FPGA/ FPGA/ FPGA/ ASIC ASIC ASIC gen gen TB' * TB TB TB' TB * TB Example: Genesis2 Example: Chisel Fast edit-sim-debug loop Slower edit-sim-debug loop Slower edit-sim-debug loop Single language for Multiple languages create Single language for structural, behavioral, + TB "semantic gap" structural + behavioral Difficult to create highly Easier to create highly Easier to create highly parameterized generators parameterized generators parameterized generators Cannot use power of host language for verification 3 / 10

Productive Multi-Level Modeling and VLSI Design Multi-Level Modeling VLSI Design SystemC Chisel HGSF Single framework for ML Hardware Generation and modeling & VLSI design Simulation Framework Fast edit-sim-debug loop Host Language HDL Single language for (Python) (Verilog) structural, behavioral, + TB synth gen DUT DUT' Easy to create highly Sim parameterized generators FPGA/ Sim ASIC Use power of host m i s TB o c language for verification 4 / 10

PyMTL PyMTL is a Python-based hardware generation and simulation framework for SoC design which enables productive multi-level modeling and VLSI implementation 5 / 10

The PyMTL Framework PyMTL PyMTL Domain Specific PyMTL Passes Language In-Memory (Python) (Python) Intermediate Representation Test & Sim Simulation Simulatable Harnesses Pass Model (Python) System Model Translation Model Elaboration Verilog Instance Pass Analysis Analysis Config Output Pass Transform New Model Pass 6 / 10

PyMTL v2 Syntax and Semantics from pymtl import * 1 s.reg_out 2 class RegIncrPRTL( Model ): 3 s.in_ s.out 4 +1 def __init__( s ): 5 s.in_ = InPort ( Bits(8) ) 6 s.out = OutPort( Bits(8) ) 7 s.temp_wire 8 s.reg_out = Wire( Bits(8) ) 9 10 @s.tick_rtl 11 def seq_logic(): 12 s.reg_out.next = s.in_ 13 14 s.temp_wire = Wire( Bits(8) ) 15 16 @s.combinational 17 def comb_logic(): 18 s.temp_wire.value = s.tmp + 1 19 20 s.connect( s.out, s.temp_wire ) 21 7 / 10

PyMTL v3 Syntax and Semantics from pymtl3 import * 1 s.reg_out 2 class RegIncrPRTL( Component ): 3 s.in_ s.out 4 +1 def construct( s ): 5 s.in_ = InPort ( Bits8 ) 6 s.out = OutPort( Bits8 ) 7 s.temp_wire 8 s.reg_out = Wire( Bits8 ) 9 10 @s.update_ff 11 def seq_logic(): 12 s.reg_out <<= s.in_ 13 14 s.temp_wire = Wire( Bits8 ) 15 16 @s.update 17 def comb_logic(): 18 s.temp_wire = s.reg_out + b8(1) 19 20 s.out //= s.temp_wire 21 8 / 10

PyMTL v3 vs Verilog Syntax and Semantics module RegIncrVRTL 1 from pymtl3 import * 1 ( 2 2 input logic clk, 3 class RegIncrPRTL( Component ): 3 input logic reset, 4 4 input logic [7:0] in_, 5 def construct( s ): 5 output logic [7:0] out 6 s.in_ = InPort ( Bits8 ) 6 ); 7 s.out = OutPort( Bits8 ) 7 8 8 logic [7:0] reg_out; 9 s.reg_out = Wire( Bits8 ) 9 10 10 always_ff @( posedge clk ) begin 11 @s.update_ff 11 reg_out <= in_; 12 def seq_logic(): 12 end 13 s.reg_out <<= s.in_ 13 14 14 logic [7:0] temp_wire; 15 s.temp_wire = Wire( Bits8 ) 15 16 16 always_comb @(*) begin 17 @s.update 17 temp_wire = reg_out + 1; 18 def comb_logic(): 18 end 19 s.temp_wire = s.reg_out + b8(1) 19 20 20 assign out = temp_wire; 21 s.out //= s.temp_wire 21 22 endmodule 23 9 / 10

PyMTL/Verilog Integration SimJITFRTL'Tool' Verilog' TranslaGon' Verilator' Source' Cache' RTL'C++' C'Shared' Source' Library' PyMTL' PyMTL' C'Interface' Wrapper' RTL'Model' TranslaGon' LLVM/GCC' CFFI'Model' Source' Gen' Instance' Instance' 10 / 10