ASIC Layout
Overview Design flow Back-end process FPGA design process Conclusions 2
ASIC Design flow 3 Source: http://www.ami.ac.uk
What is Backend? • Physical Design: 1. FloorPlanning : Architect’s job 2. Placement : Builder’s job 3. Routing : Electrician’s job 4
Input for Layout Tools Libraries : Input : • Physical Libraries (LEF/OA) • Verilog Gate Level Netlist • Cell boundaries, pins, routing rules • Timing Constraint files, for all modes (*.sdc) • Timing Libraries (*.lib) Optional Input Files : Optional Libraries : • Floorplan File • Technology Files (Cap Tables, QRC Tech file) • IO File • SI Libraries (*.cdb) • Scan Definition File
Import Design Procedure – Global Definition File File - Import Design Verilog Netlist File(s) OA-Flow Reference, Custom Libraries of Standard Cells; IOs, Custom Blocks, Rams … or LEF files (LEF/DEF Flow) Power/Ground (Special) net definitions, CPF: Common Power Format (Low-Power Design/Power Islands) Specify MMMC (Multi Mode Multi Corner) view file: links timing libraries, RC corners, and constraints per view Command: source <myfile>.globals init_design
Structure of a Die • Silicon die is mounted inside a chip package. • A die consists of a logic core inside a power ring. • Special power pads are used for the VDD and VSS (Core and Pad). 7
The Design Implementation Flow
Floorplaning • Floorplanning is a very important step in layout design. • Important objectives: Chip size Aspect ratio Placement of basic building blocks IO placement • Definition of chip size and aspect ratio along with the placement of its building blocks (memories, hard macros) strongly affects the chip routability and the final performance • The pads should be placed in a way to meet minimum pitch requirements defined by the packaging methodology 9
Placement and Routing • Placement • Routing • Defines the position of each cell • Performing the connection from the netlist between the cells (and IOs) • Placement performed in the • Metal lines are used to make the defined rows routing • Target is to place the connected • Objective is to reduce the cells into neighboring positions to interconnection length (reducing reduce the timing penalty line capacitance i.e. interconnection delay) • Global and local routing 10
Back-end Design decisions • Core and pad limited design Design size can be defined either by the core size or by the pad size. In general the design complexity is defined by the number of gates (reflected to core area) However, the pads are unproportionally big and therefore in case of great number of them, they could define the chip area • Opposite to that we have a core-limited design. • The aspect ratio of the chip has to be chosen such that it doesn’t affect the chip routability and that corresponds to packaging. The aspect ratio of 1.0 defines quadratic shape of the chip. This shape is the optimal shape in respect to placement and routing. • The size of power rings depends on estimated power consumption of the chip. Since the power pads are usually distributed evenly on all four sides of the chip, the maximum current flow through the power rings is ¼ of the total estimated current. 11
Placement • ASIC placement is performed in rows • Routing can be performed in both directions – horizontal and vertical • The chip size strongly depends on the chosen core (row) utilization. A typical value of core utilization is 75%. If the chip contains complex logic requiring excessive routing, the user should consider relaxing the core utilization. If the chip logic is relatively simple, the user may try to tighten up utilization value in order to reduce the chip size 12
Objectives of Placement Process • Performing the placement of each individual cells in the rows • Reducing the placement distance between the connected cells • Performing high density placements • Reducing the timing overhead and power consumption • Addressing the routing challenges (avoiding routing congestion congestion) • Timing driven placement tries to fulfil the timing constraints while performing placement It is connected with the processes of trial routing and RC extraction to estimate the effects of the placement choices 13
Placement Algorithms • Two general types of the algorithms: Constructive placement Iterative placement improvement. • Constructive placement method Min-cut algorithm, or eigenvalue method • Starts with a constructed solution, following iterative improvement • The min-cut algorithm placement method uses successive application of partitioning Cut the area into two pieces. Swap the cells to minimize the cost. Repeat the process, cutting smaller pieces until all the logic cells are (a) Divide the chip into bins using a grid. placed. (b) Merge all connections to the center of each bin. (c) Make a cut and swap cells between bins to minimize the cost (d) Throw out all the edges that are not inside the piece. • The eigenvalue placement algorithm uses the cost matrix or weighted (e) Repeat the process and continue the individual bins. connectivity matrix Source: Application- Specific Integrated Circuits - Michael J. S. Smith
Iterative Placement • Based on initial placement further improvements are done Selection criteria decides which cells should be moved. Measurement criteria decides whether to move the selected cells. • Several exchange methods pairwise interchange, force-directed interchange, force-directed relaxation, and force-directed pairwise relaxation. • All methods based on selecting a pair of cells which need to be exchanged. • First the examined cell is selected, after that exchange with all other random cells is evaluated based on cost criteria. The limits of selecting the pair could be defined through the Manhattan distance (a) Swapping two cells (b) Swapping more cells provides better results but It is more complex (c) A one-neighborhood. (d) A two-neighborhood. Source: Application- Specific Integrated Circuits - Michael J. S. Smith
Clock synthesis • Clock network need to be implemented to drive all sink elements (flip-flips, lathes, etc) from the same source line • Clock network consisting of large numbers of buffers, invertors, clock gates • Objective is to reduce the phase difference between the clock at the different clock sinks (clock skew) • Additional goals is to reduce the clock latency (depending on the clock tree complexity and interconnection delay) • Clock is significant source of power consumption, therefore the objective to reduce it In modern designs ~50% • Many sinks use all falling edge of the clocks Important objecting is balancing of the rise and the fall time. • The clock tree is defined in clock tree definition file 16
Clock trees • A path from the clock source to clock sinks 17 Figure source: vlsi.pro
Concept of Clock Tree Clock pad Clock tree Sub trees 18
Clock Skew • Clock skew is the maximum difference in the arrival time of a clock signal at two different sinks (flip-flops, latches etc). • Clock skew could lead to performance drop or to the need for fixing of hold time delay (adding the buffers) which results in additional power and area • Clock skew should be minimized 19 Figure source: vlsi.pro
Clock Gating and CTS • Clock gating is often used as a methodology for reducing the power consumption Clock network uses ~50% of the power budget Switching of the network when it is not needed the consumption can be dramatically reduced • Clock gating needs to be taken into consideration while making CTS Clock gate is part of the CTS and contribute to the skew CT balancing required between not-gated and gated subtrees
Routing • Goals of the routing is to minimize the interconnect delay Routing in performed using the available different layers of metal connections in the automatic way Design rules need to be fulfilled (minimum spacing etc.) Different types of routing (trial, clock routing, final routing) depending on the design phase Global routing – first phase of the final routing, connecting blocks Detailed routing – final routing of all interblock connections 21
Manhattan Routing Algorithm • Motivated by the streets of New York Straight connections in the horizontal and vertical directions Specific metal lines only for vertical or only for horizontal direction Avoiding interconnection problems Routing channels defined • Manhattan distance Summary of distance in X-axis and Y-axis direction • There are now much more advanced algorithms Pin C Pin D Metal 1 Metal 2 Pin B Pin A
Left-Edge Routing Algorithm Source: Application- Specific Integrated Circuits - Michael J. S. Smith
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