FPGA Architecture Design Architectures are usually evaluated using - - PDF document

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FPGA Architecture Design Architectures are usually evaluated using - - PDF document

May 20, 2023 114 likes •342 views

Modeling Post-Techmapping and Post-Clustering FPGA Circuit Depth Joydip Das 1 , Steven J.E. Wilton 1 , Philip Leong 2 , Wayne Luk 3 1 The University of British Columbia, 2 The Chinese University of Hong Kong, 3 Imperial College London Funded by

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SLIDE 1

Modeling Post-Techmapping and Post-Clustering FPGA Circuit Depth

Funded by Altera and NSERC

Joydip Das1, Steven J.E. Wilton1, Philip Leong2, Wayne Luk3

1The University of British Columbia, 2The Chinese University of Hong Kong, 3Imperial College London

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FPGA Architecture Design

Architectures are usually evaluated using experimental methods

  • Using tools like VPR

Problems:

  • Multi-dimensional optimization space – too much time
  • Require CAD tools for each architecture
  • Or “tuning” of a generic tool like VPR
  • No insight into what makes a good architecture
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SLIDE 2

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Can we supplement the experimental approach with analytical techniques? This talk: A model that makes it possible

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This Talk

  • 1. Motivation: Speeding up architecture design
  • 2. The model:
  • What makes a good model
  • What makes it hard
  • Overview
  • 3. Details on Depth/Delay Model
  • 4. Example of our Model’s Application
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SLIDE 3

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Accelerating FPGA Architecture Investigation

Early Architecture Evaluation Insight to Guide Experimentation

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Analytical Model

The key is an analytical model that relates architecture parameters to efficiency of the FPGA:

Delay of FPGA Implementation Depth of Critical Path in 2-LUTs

Lookup-table size, Routing parameters, etc

Area = fA(K,N,Fc....) Delay = fD(K,N,Fc,....) Power = fP(K,N,Fc....)

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SLIDE 4

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Challenge: Capturing the “essence” of programmable logic in a set of simple equations

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What makes a good model?

  • 1. Analytical Model

– No curve-fitting or expensive experimental techniques

  • 2. Balancing Complexity and Accuracy

– Simpler equations provide significantly more insight into architectural tradeoffs

  • 3. Architectural Relationships

– Should be as independent of user circuit as possible

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SLIDE 5

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Estimation vs. Modeling

Estimation: What is the performance or density of a given user circuit on an FPGA?

  • Useful in CAD tools to predict long paths, congested

regions, etc. Modeling: On average, how does an architecture parameter affect the expected speed or density of an FPGA?

  • Can we answer this independent of the user circuit?

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What makes it hard:

  • Many parameters that interact in complex ways

How we make it feasible:

  • Break the model into stages, analogous to CAD flow
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SLIDE 6

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Breaking it up: Delay

Depth of c.p. in 2-LUTs Depth of c.p. In k-LUTs # Inter-cluster connections

  • n c.p.

# Intra-cluster connections

  • n c.p.

Post-Routed Wirelength along c.p. Average Post- Placement Wirelength Delay Post-Placement Wirelength along c.p.

K, p

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Depth of c.p. in 2-LUTs Depth of c.p. In k-LUTs # Inter-cluster connections

  • n c.p.

# Intra-cluster connections

  • n c.p.

Post-Routed Wirelength along c.p. Average Post- Placement Wirelength Delay Post-Placement Wirelength along c.p.

K, p N, I, p

Breaking it up: Delay

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SLIDE 7

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Depth of c.p. in 2-LUTs Depth of c.p. In k-LUTs # Inter-cluster connections

  • n c.p.

# Intra-cluster connections

  • n c.p.

Post-Routed Wirelength along c.p. Average Post- Placement Wirelength Delay Post-Placement Wirelength along c.p.

K, p N, I, p

Breaking it up: Delay

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Depth of c.p. in 2-LUTs Depth of c.p. In k-LUTs # Inter-cluster connections

  • n c.p.

# Intra-cluster connections

  • n c.p.

Post-Routed Wirelength along c.p. Average Post- Placement Wirelength Delay Post-Placement Wirelength along c.p.

K, p N, I, p Fc, Fs, etc

Breaking it up: Delay

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SLIDE 8

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Depth of c.p. in 2-LUTs Depth of c.p. In k-LUTs # Inter-cluster connections

  • n c.p.

# Intra-cluster connections

  • n c.p.

Post-Routed Wirelength along c.p. Average Post- Placement Wirelength Delay Post-Placement Wirelength along c.p.

K, p N, I, p Fc, Fs, etc All arch. params

Breaking it up: Delay

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Depth of c.p. in 2-LUTs Depth of c.p. In k-LUTs # Inter-cluster connections

  • n c.p.

# Intra-cluster connections

  • n c.p.

Post-Routed Wirelength along c.p. Average Post- Placement Wirelength Delay Post-Placement Wirelength along c.p.

Each part is simple, but together, they relate delay-efficiency to architectural parameters

K, p N, I, p Fc, Fs, etc All arch. params

Breaking it up: Delay

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SLIDE 9

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Depth of c.p. in 2-LUTs Depth of c.p. In k-LUTs # Inter-cluster connections

  • n c.p.

# Intra-cluster connections

  • n c.p.

Post-Routed Wirelength along c.p. Average Post- Placement Wirelength Delay Post-Placement Wirelength along c.p.

Tech Mapping Clustering Routing Physical Models

This Paper:

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Depth of c.p. in 2-LUTs Depth of c.p. In k-LUTs # Inter-cluster connections

  • n c.p.

# Intra-cluster connections

  • n c.p.

Post-Routed Wirelength along c.p. Average Post- Placement Wirelength Delay Post-Placement Wirelength along c.p.

K, p

Technology Mapping Model

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SLIDE 10

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Review: Technology Mapping

Most algorithms give implementations of minimum depth Map logic gates to lookup-tables:

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Modeling Technology Mapping:

Intuitively, Bigger LUT Size Means Smaller Depth

2-LUT / Depth=4 4-LUT / Depth=2 Circuit

So, Larger LUT Size Fewer Nets Lower Depth

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SLIDE 11

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Mapping with K=4 : Two Extremes

Depth = (K – 1) = 3 [Maximum Possible] Depth = log2(K) = 2 [Minimum Possible]

Simple Approach: Take the average

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Technology Mapping Model ) ( log 1 2

2 2

γ γ − + − − = K K d d k

Depth after Techmapping Depth before Techmapping LUT Size Average Unused Inputs in Each LUT

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SLIDE 12

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Techmapping Model : Validation

Over-estimation

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Depth of c.p. in 2-LUTs Depth of c.p. In k-LUTs # Inter-cluster connections

  • n c.p.

# Intra-cluster connections

  • n c.p.

Post-Routed Wirelength along c.p. Average Post- Placement Wirelength Delay Post-Placement Wirelength along c.p.

N, I, p

Clustering Model

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SLIDE 13

Review: Clustering / Packing

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FPGA logic blocks usually contain several LUTs: Altera: LABs Xilinx: CLBs Goal of Clustering Algorithms: Group LUTs into LAB-sized clusters

  • Connections between LUTs within a cluster are fast

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Clustering does not eliminate nets:

  • It just makes some nets local (intra-cluster)

and some global (inter-cluster) Intuitively: the larger the cluster size, the more nets are made local. Goal: derive an equation for the proportion of nets along the critical path that are made local

Clustering Model

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SLIDE 14

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Sketch of derivation:

  • 1. Some nets are made local “on purpose”
  • 2. Some nets are made local “by chance”
  • These are not nets that are specifically targeted

by the cluster algorithm Work out proportion of each and combine them

Clustering Model

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Connections on Critical Path – Primary Goal

LUT-1 LUT-1 LUT-3 LUT-2 LUT-4 LUT-5

Cluster Size, c = 5

LUT-2 LUT-3 LUT-4 LUT-5 LUT-6 LUT-7

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SLIDE 15

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Connections on Critical Path – Primary Goal

LUT-1 LUT-1 LUT-3 LUT-2 LUT-4 LUT-5

Cluster Size, c = 5

LUT-2 LUT-3 LUT-4 LUT-5 LUT-6 LUT-7

) 1 ( / − = = c Local Absorbed c Size Cluster

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Connections Absorbed: Not on Critical Path – by chance

LUT-1 LUT-1 LUT-3 LUT-2 LUT-4 LUT-5

Cluster Size, c = 5

LUT-2 LUT-3 LUT-4 LUT-5 LUT-6 LUT-7

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SLIDE 16

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Connections Absorbed: Not on Critical Path – by chance

LUT-1 LUT-1 LUT-3 LUT-2 LUT-4 LUT-5

Cluster Size, c = 5

LUT-2 LUT-3 LUT-4 LUT-5 LUT-6 LUT-7

[ ]

1 ) ( : + − − c K c k n c chance by Absorbed γ

Details of derivation can be found in our paper

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Which leads to

[ ]

c k k k c

n n c where K c c K c n c c d d = ⎥ ⎥ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎢ ⎢ ⎣ ⎡ − + − − + − = , ) ( 1 ) ( ) 1 ( γ γ

Clustering Model:

Details of derivation can be found in our paper

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SLIDE 17

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Clustering Model : Validation

LUT Size, K=4 LUT Size, K=6

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Is our Model Actually Useful?

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SLIDE 18

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We considered two flows: The “shape” of the results is more important than the actual values

Example of Model’s Application

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Critical Path Delay from Analytical Model

Analytical Flow

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SLIDE 19

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Intra-Cluster & Inter-Cluster Delay:

Intra-Cluster Delay (t_intra) Inter-Cluster Delay (t_inter)

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Critical Path Delay from Analytical Model

Analytical Flow

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SLIDE 20

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Important caveat: We do not yet have a model for delay routing For now, we use experimental results for this part

Depth of c.p. in 2-LUTs Depth of c.p. In k-LUTs # Inter-cluster connections

  • n c.p.

# Intra-cluster connections

  • n c.p.

Post-Routed Wirelength along c.p. Average Post- Placement Wirelength Delay Post-Placement Wirelength along c.p.

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Overall Results: Delay

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SLIDE 21

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Same Conclusion in both cases: K=4.

Overall Results: Delay

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Key Result: It is possible to describe an FPGA architectures using a set of simple equations This Talk:

  • Analytical model for techmapped & clustered depth
  • Example of model’s application for early stage

architecture evaluation Ongoing Works:

  • Analytical model for post-routing delay
  • Investigation of "Discrete Effects"
  • Analytical model for the whole design flow

Summary