Digital Signal Processing for the APFEL Oliver Noll - - PowerPoint PPT Presentation

digital signal processing for the apfel
SMART_READER_LITE
LIVE PREVIEW

Digital Signal Processing for the APFEL Oliver Noll - - PowerPoint PPT Presentation

Digital Signal Processing for the APFEL Oliver Noll PANDA-Collaboration Meeting 18/3 November 2018 1 APFEL ASIC Feature Extraction 2 Integration of Feature Extraction into SADC 3 MAMI Beamtest with SADC Digital Signal Processing Example


slide-1
SLIDE 1

Digital Signal Processing for the APFEL

Oliver Noll

¯ PANDA-Collaboration Meeting 18/3

November 2018

slide-2
SLIDE 2

1 APFEL ASIC Feature Extraction 2 Integration of Feature Extraction into SADC 3 MAMI Beamtest with SADC

slide-3
SLIDE 3

Digital Signal Processing

Properties

Hit detection Time Energy (pulse height)

Requirements on Feature Extr.

Fast (calculation time) Sensitive to ASIC pulse shape Linear Threshold as low as possible Dead time as short as possible

5 10 15 20 Time [μs] 14000 14500 15000 15500 Signal [a.u.]

Example Pulse, 450 MeV CC

Height Time

5 10 15 20 Time [μs] 20 15 10 5 5 10 Signal [a.u.]

Example Pulse, Very Tiny

Height ? TIME ?

APFEL ASIC Feature Extraction Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 1/25

slide-4
SLIDE 4

Digital Signal Processing

Filter

Modification of transfer function Suppression of HF noise ⇒ smoothing

Feature Extraction

Determination of amplitude T0 determination Pileup detection/correction

1100 1150 1200 1250 1300 1350 1400 1450 1500 Amplitude [a.u.] 500 1000 1500 2000 Events

σ µ = 0.56 %

∼ 150 MeV

Spectrum of 10000 ASIC Testpulses TMAX Amplitude Extraction on FPGA

APFEL ASIC Feature Extraction Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 2/25

slide-5
SLIDE 5

Filter (smoothing)

Analog System Digital System

f(t) g(t) fm gm

APFEL ASIC Feature Extraction Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 3/25

slide-6
SLIDE 6

Smoothing via Finite Impulse Response (FIR) Filter

Idea

Transfer function suppressed HF noise (low pass) Z transformation of impulse response H(z) = N

n=0 h(n) · z−n

h(n) : Filter Koeffizienten z = eiωT Each output value is weighted sum of most recent input values

  • ut[n] = h0in[n] + h1in[n − 1] + ... + hNin[n − N]

h0 h1 h2 h3 z-1 + + + z-1 z-1 hN + z-1 0,0,1,0,0,0,0,... 0,0,h1,h2,h3,...,hN,0 Multiplier One sample delay and register (Tap) Adder

APFEL ASIC Feature Extraction Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 4/25

slide-7
SLIDE 7

Smoothing via Finite Impulse Response (FIR) Filter

5 10 15 20 25 30 35 40

  • Freq. [MHz]

50 40 30 20 10 Attenuation [dB]

25 Taps, 80.0 MS/s fs/2 = 40.0 MHz Pass Band (0-8 MHz)

  • Trans. Band (8-16 MHz)

Stop Band (16-40.0 MHz)

APFEL ASIC Feature Extraction Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 5/25

slide-8
SLIDE 8

Smoothing via Finite Impulse Response (FIR) Filter

60 80 100 120 140 160 180 200 Time [Sample] 50 40 30 20 10 10 Amplitude [a.u.]

FIR Filter Example 25 Taps Raw Trace FIR Smoothing

APFEL ASIC Feature Extraction Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 6/25

slide-9
SLIDE 9

Smoothing via Finite Impulse Response (FIR) Filter

Benefits

Reliable smoothing procedure (stable, no self-excitation) No pulse washout (pulse slope) Best way to increase signal/noise ratio

Drawback

FIR filtering eats FPGA recourses

APFEL ASIC Feature Extraction Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 7/25

slide-10
SLIDE 10

Smoothing via Finite Impulse Response (FIR) Filter

h0 h1 h2 h3 z-1 + + + z-1 z-1 hN + z-1 0,0,1,0,0,0,0,... 0,0,h0,h1,h2,h3,...,hN Multiplier One sample delay and register (Tap) Adder

Implementation

Efficient synthesis with Digital Signal Processing slices (DSP) ∼1 DSP slices per tap, 25 taps · 32 channel 800 DSP slices 600 DSP slices on XC7K160T Need of resource saving implementation

APFEL ASIC Feature Extraction Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 8/25

slide-11
SLIDE 11

Implementation with Distributed Arithmetic

Idea: Using Look Up Tables (LUT) instate of multiplication slices y =

K

  • k=0

hk · xk xk =

N

  • n=0

bkn2n ... y =

N

  • n=0

K

  • k=0

hk · bkn

  • 2n

Precalculated and stored in Look Up Tables (LUT)

APFEL ASIC Feature Extraction Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 9/25

slide-12
SLIDE 12

FIR with Distributed Arithmetic

VHDL Generator

Software package which generates hardware description Free choose of parameters

Number of taps Samplingrate Pass-/stopband Fix point resolution ...

Hardware Simulation

GHDL testbench Timing integrity

APFEL ASIC Feature Extraction Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 10/25

slide-13
SLIDE 13

Time Measurement and Amplitude EXtraction (TMAX)

TMAX Amplitude Path

Sensitive to rising edge Cancels out falling edge No overshoot Baseline subtraction

Derivative: D[i] = T[i + r] − T[i] Heaviside function Θ: x →

  • 0 :

x < 0 1 : x ≥ 0 TMAX: FTMAX =

N

  • i=0

D[i] − Θ[−D[i]] · D[i]

5 10 15 20 Time [μs] 14000 14500 15000 15500 Signal [a.u.]

Example Pulse, 450 MeV CC r

5 10 15 Time [µs] 5000 4000 3000 2000 1000 1000 Filter [a.u.]

TMAX Filter, 450 MeV CC Raw Signal TMAX

APFEL ASIC Feature Extraction Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 11/25

slide-14
SLIDE 14

Time Measurement and Amplitude EXtraction (TMAX)

TMAX Time Path

T0 at maximum Linear interpolation between samples Implementation with LUT

Derivative: D[i] = T[i + r] − T[i] Time at change of sign: i0 and i1 Linear Interpolation T0 = i0 +

D[i0] D[i0]−D[i1]

80 100 120 140 160 180 200 Time [Sample] 60 40 20 20 40 60 Amplitude [MeV]

Filter Example 50 MeV Signal Raw Trace FIR Smoothing Time Derivative Extracted Ampl. T0

80 100 120 140 160 180 Time [Sample] 6 4 2 2 4 6 Amplitude [MeV]

Filter Example 5 MeV Signal Raw Trace FIR Smoothing Time Derivative Extracted Ampl. T0

APFEL ASIC Feature Extraction Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 12/25

slide-15
SLIDE 15

Time Measurement and Amplitude EXtraction (TMAX)

Is it worth all the effort?

¯ PANDA operates triggerless FIR improves time resolution: better time resolution → better energy resolution

100 200 300 400 500 600 700 800 900 Signal [MeV] 5 10 15 20 25 30 35 40 Time Resolution [ns]

Time Resolution Simulation No FIR Simulation FIR 25 Taps

100 200 300 400 500 600 700 800 900 Signal [MeV] 1 2 3 4 5 Time Resolution [ns]

Time Resolution Simulation No FIR Simulation FIR 25 Taps

APFEL ASIC Feature Extraction Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 13/25

slide-16
SLIDE 16

Integration of Feature Extraction into SADC

Integration of Feature Extraction into SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 14/25

slide-17
SLIDE 17

Integration of Feature Extraction into SADC

Bonn Firmware

Johannes M¨ ullers HISKP, Bonn Firmware for Crystal Barrel GitLab repository Meetings in Bonn Helping hand

ADC SMA Smoothing Feature Extraction External Trigger Package Builder UDP Infrastructure Gbit Interface

x 32 Integration of Feature Extraction into SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 15/25

slide-18
SLIDE 18

Integration of Feature Extraction into SADC

Mainz Firmware

Using Bonn infrastructure Triggerless FIR filtering TMAX feature extraction New data package concept Full hardware simulation

ADC FIR Smoothing TMAX External Trigger Package Builder UDP Infrastructure Gbit Interface

x 32

Arbiter

Integration of Feature Extraction into SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 16/25

slide-19
SLIDE 19

MAMI Beamtest with SADC

MAMI Beamtest with SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 17/25

slide-20
SLIDE 20

MAMI Beamtest with SADC

Setup

PROTO16-2 (4x4) SADC with Mainz firmware Triggerless Reference scintillator

Measuring Program

Energies: 195,450,855 MeV Different APD gains Central shot in every crystal

Linearity Energy resolution

Rate scan (up to 400 kHz) FIR tap scan

MAMI Beamtest with SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 18/25

slide-21
SLIDE 21

Single Spectra Example

MAMI Beamtest with SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 19/25

slide-22
SLIDE 22

Sum Spectra Example

MAMI Beamtest with SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 20/25

slide-23
SLIDE 23

Linearity

200 400 600 800 1000 1000 2000 3000 4000 5000 6000 7000 Sum Filter Value [a.u.]

Crystal 0 a = 5.91±0.02 b = -51.87±10.30 χ2/dof = 28.85 / 1

200 400 600 800 1000 1000 2000 3000 4000 5000 6000 7000

Crystal 1 a = 5.86±0.00 b = -80.08±1.86 χ2/dof = 1.05 / 1

200 400 600 800 1000 1000 2000 3000 4000 5000 6000 7000

Crystal 2 a = 5.80±0.02 b = -72.14±9.10 χ2/dof = 26.41 / 1

200 400 600 800 1000 1000 2000 3000 4000 5000 6000 7000

Crystal 3 a = 5.67±0.05 b = -72.21±23.78 χ2/dof = 215.74 / 1

200 400 600 800 1000 1000 2000 3000 4000 5000 6000 7000 Sum Filter Value [a.u.]

Crystal 4 a = 5.90±0.00 b = -85.25±2.12 χ2/dof = 3.04 / 1

200 400 600 800 1000 1000 2000 3000 4000 5000 6000 7000

Crystal 5 a = 6.07±0.10 b = -48.23±58.14 χ2/dof = 1311.49 / 1

200 400 600 800 1000 1000 2000 3000 4000 5000 6000 7000

Crystal 6 a = 6.06±0.09 b = -54.28±54.28 χ2/dof = 1017.8 / 1

200 400 600 800 1000 1000 2000 3000 4000 5000 6000 7000

Crystal 7 a = 5.88±inf b = -101.33±inf χ2/dof = 0.0 / 0

200 400 600 800 1000 1000 2000 3000 4000 5000 6000 7000 Sum Filter Value [a.u.]

Crystal 8 a = 5.79±0.02 b = -57.89±12.48 χ2/dof = 47.56 / 1

200 400 600 800 1000 1000 2000 3000 4000 5000 6000 7000

Crystal 9 a = 6.16±0.08 b = -66.56±40.06 χ2/dof = 1099.28 / 1

200 400 600 800 1000 1000 2000 3000 4000 5000 6000 7000

Crystal 10 a = 6.13±0.10 b = -47.57±51.31 χ2/dof = 1473.78 / 1

200 400 600 800 1000 1000 2000 3000 4000 5000 6000 7000

Crystal 11 a = 6.00±0.03 b = -14.95±13.46 χ2/dof = 62.62 / 1

200 400 600 800 1000 Energy [MeV] 1000 2000 3000 4000 5000 6000 7000 Sum Filter Value [a.u.]

Crystal 12 a = 5.85±0.12 b = -10.02±58.08 χ2/dof = 1340.96 / 1

200 400 600 800 1000 Energy [MeV] 1000 2000 3000 4000 5000 6000 7000

Crystal 13 a = 5.98±0.00 b = -60.78±1.74 χ2/dof = 2.08 / 1

200 400 600 800 1000 Energy [MeV] 1000 2000 3000 4000 5000 6000 7000

Crystal 14 a = 5.92±0.00 b = -66.33±0.04 χ2/dof = 0.0 / 1

200 400 600 800 1000 Energy [MeV] 1000 2000 3000 4000 5000 6000 7000

Crystal 15 a = 5.57±0.01 b = -19.95±4.57 χ2/dof = 7.67 / 1

MAMI Beamtest with SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 21/25

slide-24
SLIDE 24

Relative Energy Resolution

200 300 400 500 600 700 800 900 2 4 6 8 10 12 rel en. res. [%]

Crystal 0

σE E (1GeV) = 3.92 % 200 300 400 500 600 700 800 900 2 4 6 8 10 12

Crystal 1

σE E (1GeV) = 3.47 % 200 300 400 500 600 700 800 900 2 4 6 8 10 12

Crystal 2

σE E (1GeV) = 3.62 % 200 300 400 500 600 700 800 900 2 4 6 8 10 12

Crystal 3

σE E (1GeV) = 4.25 % 200 300 400 500 600 700 800 900 2 4 6 8 10 12 rel en. res. [%]

Crystal 4

σE E (1GeV) = 2.97 % 200 300 400 500 600 700 800 900 2 4 6 8 10 12

Crystal 5

σE E (1GeV) = 2.42 % 200 300 400 500 600 700 800 900 2 4 6 8 10 12

Crystal 6

σE E (1GeV) = 2.28 % 200 300 400 500 600 700 800 900 2 4 6 8 10 12

Crystal 7

σE E (1GeV) = 3.43 % 200 300 400 500 600 700 800 900 2 4 6 8 10 12 rel en. res. [%]

Crystal 8

σE E (1GeV) = 3.13 % 200 300 400 500 600 700 800 900 2 4 6 8 10 12

Crystal 9

σE E (1GeV) = 2.1 % 200 300 400 500 600 700 800 900 2 4 6 8 10 12

Crystal 10

σE E (1GeV) = 2.14 % 200 300 400 500 600 700 800 900 2 4 6 8 10 12

Crystal 11

σE E (1GeV) = 3.55 % 200 300 400 500 600 700 800 900 Energy [MeV] 2 4 6 8 10 12 rel en. res. [%]

Crystal 12

σE E (1GeV) = 3.51 % 200 300 400 500 600 700 800 900 Energy [MeV] 2 4 6 8 10 12

Crystal 13

σE E (1GeV) = 2.65 % 200 300 400 500 600 700 800 900 Energy [MeV] 2 4 6 8 10 12

Crystal 14

σE E (1GeV) = 2.72 % 200 300 400 500 600 700 800 900 Energy [MeV] 2 4 6 8 10 12

Crystal 15

σE E (1GeV) = 3.74 %

MAMI Beamtest with SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 22/25

slide-25
SLIDE 25

Rate scan

MAMI Beamtest with SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 23/25

slide-26
SLIDE 26

Rate scan

50 100 150 200 250 300 350 400 Scintillator Rate [kHz] 50 100 150 200 250 300 350 400 Detector Rate [kHz]

Rates RDet(RSci, τ, c) =

RSci 1 + τRSci + c

Detector Rate

With τ = 400 ns and c = 5 kHz

MAMI Beamtest with SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 24/25

slide-27
SLIDE 27

Conclusion

Development of APFEL feature extraction is finished Performance tested with hardware and software simulations First implementation into SADC Successful beamtest at MAMI

MAMI Beamtest with SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 25/25

slide-28
SLIDE 28

Backup

MAMI Beamtest with SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 25/25

slide-29
SLIDE 29

FIR with Distributed Arithmetic

x0: 0011111010010 x2: 0011111011000 x3: 0011111010011 x4: 0011111011010 . . . xK: 0011111011110

Bit Shift Register (BSR) 00000000...00000 => v0 00000000...00001 => v1 00000000...00010 => v2 00000000...00011 => v3 . . . 0010…………… 0 => vs . . . 11111111...11111 => vn LUT 2 ( L S B ) 25 Bit Shift Register (BSR) Bit Shift Register (BSR) Bit Shift Register (BSR) Bit Shift Register (BSR) vs << 0 + … << 1 + … << 2 + . . + v0 << 5 + . . + vx << MSB Adder Y

y = N

n=0

K

k=0 hk · bkn

  • 2n

MAMI Beamtest with SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 25/25

slide-30
SLIDE 30

FIR with Distributed Arithmetic

00000000...00000 => v0 00000000...00001 => v1 00000000...00010 => v2 00000000...00001 => v3 00000000...00101 => v4 00000000...00111 => v5 00000000...00000 => v6 00000000...00001 => v7 00000000...00010 => v8 00000000...00001 => v9 00000000...00101 => v10 00000000...00111 => v11 00000000...00000 => v12 00000000...00001 => v13 00000000...00010 => v14 00000000...00001 => v15 00000000...00101 => v16 00000000...00111 => v17 . . . 0010…………… 0 => vs . . . 11111111...11111 => vn LUT 000000 => val_(v0+v1+v2+v3+v4+v5)_0 000001 => val_(v0+v1+v2+v3+v4+v5)_1 000010 => val_(v0+v1+v2+v3+v4+v5)_2 000011 => val_(v0+v1+v2+v3+v4+v5)_3 000100 => val_(v0+v1+v2+v3+v4+v5)_4 000101 => val_(v0+v1+v2+v3+v4+v5)_5 . . LUT_0 (6 bit) 000000 => val_(v6+v7+v8+v9+v10+v11)_0 000001 => val_(v6+v7+v8+v9+v10+v11)_1 000010 => val_(v6+v7+v8+v9+v10+v11)_2 000011 => val_(v6+v7+v8+v9+v10+v11)_3 000100 => val_(v6+v7+v8+v9+v10+v11)_4 000101 => val_(v6+v7+v8+v9+v10+v11)_5 . . LUT_1 (6 bit) 000000 => val_(v12+v13+v14+v15+v16+v17)_0 000001 => val_(v12+v13+v14+v15+v16+v17)_1 000010 => val_(v12+v13+v14+v15+v16+v17)_2 000011 => val_(v12+v13+v14+v15+v16+v17)_3 000100 => val_(v12+v13+v14+v15+v16+v17)_4 000101 => val_(v12+v13+v14+v15+v16+v17)_5 . . LUT_2 (6 bit) . . . LUT_i (6 bit)

+

Pre Adder v0 v1 v2 v3 . . . vn vs << 0 + … << 1 + … << 2 + . . + v0 << 5 + . . + vx << MSB

Y

MAMI Beamtest with SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 25/25

slide-31
SLIDE 31

MAMI Beamtest with SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 25/25

slide-32
SLIDE 32

MAMI Beamtest with SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 25/25

slide-33
SLIDE 33

MAMI Beamtest with SADC Oliver Noll ¯ PANDA-Collaboration Meeting 18/3 25/25