Digital Hilbert Transformers for FPGA-based Phase-Locked Loops - - PowerPoint PPT Presentation

Motivation Hilbert Transform Implementation Results

Digital Hilbert Transformers for FPGA-based Phase-Locked Loops

Martin Kumm, M. Shahab Sanjari

Gesellschaft f¨ ur Schwerionenforschung mbH Department of Synchrotron Radio Frequency Darmstadt, Germany

September 9, 2008

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results

Content

1

Motivation

2

Hilbert Transform

3

Implementation

4

Results

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results Controlling the phase in accelerating cavities Phase-locked loop Phase detection

The Problem: Phase detection in a particle accelerator

The Problem A 180◦ phase difference is necessary for acceleration Accelerating cavities drift in phase ➯ Using active control ➯ Exact phase measurement needed Frequency is varying during acceleration (0.8...5.4 MHz)

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results Controlling the phase in accelerating cavities Phase-locked loop Phase detection

Phase-locked loop (PLL)

Location of the PLL A frequency change to a constant intermediate frequency (IF) is necessary A tracked offset local oscillator (LO) is needed This is done with an “all-digital” phase-locked loop within an FPGA A “direct digital synthesizer” (DDS) is used for signal generation ➯ Main challenge: phase detection (PD)

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results Controlling the phase in accelerating cavities Phase-locked loop Phase detection

Phase detection with a real signal

The Problem We have: s(n) = ˆ u cos(Ωn + φ0) (Ω = 2πf /fs) We want: ϕ(n) = Ωn + φ0 The direct way: ϕ(n) = 1

ˆ u arccos(s(n))

not unique for all amplitudes amplitude dependent better: using Hilbert transform

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results Controlling the phase in accelerating cavities Phase-locked loop Phase detection

Phase detection with an analytic signal

Extending s(n) with an imaginary component H{s(n)} results in s(n) = s(n) + jH{s(n)} = ˆ u[cos(Ωn + φ0) + j sin(Ωn + φ0)] = ˆ uej(Ωn+φ0) We obtain the so called “analytic signal” Then: ϕ(n) = arctan( Im{s(n)}

Re{s(n)})

Efficient FPGA computation possible with CORDIC Algorithm ➯ How to build an analytic signal?

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results Hilbert Transform Principle Architectures for the Hilbert Transform

Hilbert Transform Principle

The Hilbert transform can be defined using a convolution: H{s(n)} = s(n) ⊛ hH(n) ➯ It can be seen as a digital filter with a transfer function HH(ejΩ) =

    

j for −π < Ω < 0 for Ω = 0 −j for 0 < Ω < π The magnitude response is unity (exept for Ω = 0) The phase response is +90◦ for positive and −90◦ for negative frequencies The analytic signal s(n) + jH{s(n)} has no signal components for negative frequencies

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results Hilbert Transform Principle Architectures for the Hilbert Transform

Architectures for the Hilbert Transform

Possible architectures

1 90◦ phase splitting network

➯ Special case: FIR filter for imaginary part

2 Complex filter Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results Hilbert Transform Principle Architectures for the Hilbert Transform

Architectures for the Hilbert Transform

Possible architectures

1 90◦ phase splitting network

➯ Special case: FIR filter for imaginary part

2 Complex filter Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results FIR Implementation Consequences of the amplitude error Frequency Sampling Filter

FIR Implementation - Structure of the Filter

FIR Implementation Impulse response has

1

an odd symmetry and

2

all even coefficients are zero

➯ Fast and efficient implementation possible ➯ An 11-Tap FIR filter was implemented

−6 −4 −2 2 4 6 −0.8 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 hH(n) n

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results FIR Implementation Consequences of the amplitude error Frequency Sampling Filter

FIR Implementation - Magnitude and Phase Response

−0.5 0.5 −20 −15 −10 −5 5 |HH(ej ω)| f/fs

Figure: Magnitude Response

−0.5 0.5 −150 −100 −50 50 100 150 arg HH(ej ω) f/fs

Figure: Phase Response

➯ The amplitude response is an approximation to 0 dB ➯ The phase response is exactly ±90◦

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results FIR Implementation Consequences of the amplitude error Frequency Sampling Filter

FIR Implementation - Consequences of the amplitude error

The gain of the imaginary path

• f the total filter is varying ...

... while the real part of the filter (z−D) is constant ➯ The vector in the complex plane forms an ellipse rather than a circle ➯ This causes a dynamic phase error, which can be analytically determined from the amplitude gain error (Ge) to be maximal ∆ϕmax(Ge) = π

2 − 2 arcsin

• Ge

1+Ge ; (∆ϕ = ϕ′ − ϕ)

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results FIR Implementation Consequences of the amplitude error Frequency Sampling Filter

FIR Implementation - Total Phase and Phase Error

−300 −200 −100 100 200 300 −150 −100 −50 50 100 150 arg x, [°] φ [°] Ge=1 Ge=0.707 Ge=0.1

Figure: Total Phase

−300 −200 −100 100 200 300 −1 −0.5 0.5 1 (arg x,−arg x)/∆ϕmax φ [°] Ge=1 Ge=0.707 Ge=0.1

Figure: Phase Error

➯ Mean error is zero, base frequency is twice the signal frequency ➯ Phase error can be cancelled by filtering (PLL loop bandwidth ≪ signal frequency)

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results FIR Implementation Consequences of the amplitude error Frequency Sampling Filter

FIR Implementation - Filter for Cancelling the Phase Error

Transforming an continous low-pass filter FLP(s) =

1 1+sTc

to a discrete filter leads to FLP(z) =

b0 1+a1z−1 (rectangle

method ) Defining b0 := 2−M results in a1 = 2−M − 1 ➯ no multipliers needed, efficient FPGA implementation possible Cut-off frequency is fc =

fs 2M−1

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results FIR Implementation Consequences of the amplitude error Frequency Sampling Filter

FIR Implementation - Frequency response of low-pass filter

10

−3

10

−2

10

−1

10 −100 −80 −60 −40 −20 |FLP(ejω)| [dB] f/fs N=1 N=3 N=4 N=8

Using N filters in series improves the attenuation

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results FIR Implementation Consequences of the amplitude error Frequency Sampling Filter

Architectures for the Hilbert Transform

Possible architectures

1 90◦ phase splitting network

➯ Special case: FIR filter for imaginary part

2 Complex filter Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results FIR Implementation Consequences of the amplitude error Frequency Sampling Filter

Frequency Sampling Filter (FSF) - Idea

FSF Idea FSF are a generalization of “cascaded integrator comb” (CIC) filters Usually used as decimation filter (see e.g. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, Springer, 2007) Idea:

A basic comb filter of the form F(z) = 1 − z−Nc produces zeros at multiple angles of Ω = 360◦

Nc

Additional IIR pole filters are chosen to cancel undesired zeros

Using simple coefficients from the set {−1, 0, 1} results in hardware efficient filters

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results FIR Implementation Consequences of the amplitude error Frequency Sampling Filter

Frequency Sampling Filter (FSF) - Example (1)

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

100 200 300 −40 −30 −20 −10 10 Ω [°] 100 200 300 −20 −10 10 20 30 40 Ω [°]

Motivation Hilbert Transform Implementation Results FIR Implementation Consequences of the amplitude error Frequency Sampling Filter

Frequency Sampling Filter (FSF) - Example (2)

➯ Resulting filter is a real bandpass filter

100 200 300 −40 −30 −20 −10 10 20 Ω [°] Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results FIR Implementation Consequences of the amplitude error Frequency Sampling Filter

Frequency Sampling Filter (FSF) - Pole Filters

Usefull coefficients for pole filter CΩ(z) a1 a2 a3 Ω1 Ω2 C0(z) −1 0◦ C180(z) 1 180◦ C±60(z) −1 1 ±60◦ C±90(z) 1 ±90◦ C±120(z) 1 1 ±120◦ C0/180(z) −1 0◦/180◦ Remember that we want to design a filter for the Hilbert transform! ➯ Negative frequencies have to be attenuated Solution: Extending the coefficient range to imaginary values

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results FIR Implementation Consequences of the amplitude error Frequency Sampling Filter

Frequency Sampling Filter (FSF) - Complex Pole Filters

Useful complex coefficients for pole filter CΩ(z) a1 a2 a3 Ω1 Ω2 C+90(z) −j +90◦ C−90(z) j −90◦ C+30/+150(z) −j −1 +30◦ +150◦ C−30/−150(z) j −1 −30◦ −150◦ C0/+90/180(z) −j −1 j 0◦/180◦ +90◦ Practical Implementation A multiplication of a complex value with j can be realized by negating the real part and swapping the real and imaginary part afterwards: (a + jb) · j = −b + ja

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results FIR Implementation Consequences of the amplitude error Frequency Sampling Filter

Resulting Frequency Responses

Filters with different performance and complexities were successfully implemented in VHDL and synthesized for an Altera Cyclone FPGA (EP1C6Q240C8)

−0.5 0.5 −60 −50 −40 −30 −20 −10 f/fs |HA2−4(ejΩ)| [dB] HA2 HA3 HA4

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results FIR Implementation Consequences of the amplitude error Frequency Sampling Filter

Implementation Structure of HA4

Example of the FPGA implementation of the most complex filter HA4.

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results Summary of the implemented filters Conclusion

Results

Performance and ressource consumption of the implemented filters Filter Gstop/dB ∆Gpass/dB NA NR NLE fmax/MHz FLP(z) 18

• 6

6 153 142 HA1(z) 20.7

• 0.5...0.76

10 6 337 266 HA2(z) 11.3 3 3 4 110 275 HA3(z) 47.7 3 16 18 562 191 HA4(z) 44.6

• 0.005...0

18 38 679 193 Used symbols: Gstop: stopband attenuation, ∆Gpass: passband ripple, NA, NR and NLE: required number of adders/subtracters (incl. output register), registers (incl. pipeline registers) and logic elements, fmax: maximum speed.

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results Summary of the implemented filters Conclusion

Conclusion

Different architectures for the Hilbert transform were implemented with various performance and complexitiy ... and were sucessfully used within a phase-locked loop application An analytical expression for the resulting phase error was formulated An efficient IIR low-pass filter that is able to supress the phase error was proposed A novel method for the design of complex, multiplier-less frequency sampling filters was presented

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs

Motivation Hilbert Transform Implementation Results Summary of the implemented filters Conclusion

End

Thank you for your attention!

Martin Kumm, M. Shahab Sanjari Digital Hilbert Transformers for FPGA-based PLLs