Designing Smart Sensors In Standard CMOS Kofi Makinwa Electronic - PowerPoint PPT Presentation

Designing Smart Sensors In Standard CMOS Kofi Makinwa Electronic Instrumentation Laboratory/DIMES Delft University of Technology Delft, The Netherlands

Sensors are Everywhere! Sept 2007 ESSCIRC 07 2

World Sensor Market US $Billions 50.6 42.2 32.5 Time 1998 2003 2008 Courtesy of InTechno Consulting Sept 2007 ESSCIRC 07 3

Traditional Sensor Systems Interface Sensor electronics traditional wind sensor Sept 2007 ESSCIRC 07 4

Smart Sensors Interface Sensor Electronics smart wind sensor • Sensor + Interface electronics in one package • Robust microprocessor compatible interface Sept 2007 ESSCIRC 07 5

Why Smart Sensors? • Standard output format ⇒ plug-and-play! • Bus interfaces ⇒ multiple sensors, less wiring • More functionality: self-test, diagnostics, storage of sensor ID and calibration data • Smaller, cheaper, more reliable … Sept 2007 ESSCIRC 07 6

Smart Sensor Design Sensors • Cover many domains ⇒ sensor physics Package • Interact with the environment ⇒ package design Interface Electronics • Output small analog signals ⇒ analog design Smart sensor design is challenging! Sept 2007 ESSCIRC 07 7

Sensors in Standard CMOS Standard CMOS sensors cover the following domains: • Thermal ⇒ resistors, transistors & thermopiles • Magnetic ⇒ Hall-plates & magFETs • Optical ⇒ photo-diodes • Chemical ⇒ ISFETs • Electrical ⇒ resistors, capacitors & inductors • Mechanical (requires micro-machining!) ⇒ moveable proof mass or diaphragm Note: Silicon sensors are usually not best in class! Ultimate performance ⇒ “exotic” sensor + CMOS circuitry Sept 2007 ESSCIRC 07 8

Typical Sensor Characteristics In general, sensors • Output small analog quantities: microvolts (Hall sensors, thermopiles), microamps (photodiodes), atto-farads (inertial sensors) • Are relatively slow – at least compared to the switching speed of transistors In addition, silicon sensors • Are sensitive to process spread , temperature & (packaging) stress Sept 2007 ESSCIRC 07 9

A Design Methodology Do no harm! ⇒ sensor should limits performance 1. Do system design! ⇒ use sensor physics to 2. compensate for sensor non-idealities Digitize early! ⇒ less analog errors, digital signal 3. processing (flexibility, Moore’s Law) 4. Be dynamic! Use DEM, chopping, auto-zeroing and Σ∆ modulation to shift gain errors,1/ f noise, offset and quantization noise out of (LF) sensor bandwidth dB Shifted offset, gain error, Sensor 1/ f noise, Q-noise BW freq. Sept 2007 ESSCIRC 07 10

A Design Methodology Do no harm! ⇒ sensor should limits performance 1. Do system design! ⇒ use sensor physics to 2. compensate for sensor non-idealities Digitize early! ⇒ less analog errors, digital signal 3. processing (flexibility, Moore’s Law) 4. Be dynamic! Use DEM, chopping, auto-zeroing and Σ∆ modulation ⇒ reduce gain errors,1/ f noise, offset and quantization noise in small sensor bandwidth Three case studies: a smart wind sensor, a smart Hall-effect sensor and a smart temperature sensor Sept 2007 ESSCIRC 07 11

A Smart Wind Sensor! Convective cooling ⇒ temperature gradient ⇒ wind speed and direction Sept 2007 ESSCIRC 07 12

An Electronic Wind Sensor Sept 2007 ESSCIRC 07 13

Wind Sensor Chip • On-chip heaters • PNP: measures chip temperature T chip • Thermopiles: measure temperature differences δ T NS and δ T EW ⇒ wind speed and direction Sept 2007 ESSCIRC 07 14

Sensor Characteristics • Slow (~1s time constant) • Thermopile output is small (microvolts) and spreads • Output is proportional to ∆ T = T chip - T amb ⇒ regulation • Sensor suffers from packaging offset (chip is not perfectly centered on disc) ⇒ calibration and trimming • Sensor achieves ~1 ° angle error ⇒ thermopile outputs must be digitized with > 8-bit resolution • Characteristics depend on chip size ⇒ same chip area ⇒ simple interface circuitry Sept 2007 ESSCIRC 07 15

Thermal Balancing • Old principle: measure temperature difference δ T • New principle: cancel temperature differences • Measure difference in heater power δ P ⇒ wind speed & direction Sept 2007 ESSCIRC 07 16

Thermal Σ∆ Modulation • Heaters are pulsed by bitstream • Pulses are thermally low-pass filtered ⇒ δ T NS ~ 0 • Requires only a low- offset comparator! • Another modulator regulates ∆ T Sept 2007 ESSCIRC 07 17

Smart Wind Sensor Sept 2007 ESSCIRC 07 18

Smart Wind Sensor Chip • Same area as original sensor • Even in a 1.6µm CMOS process! • Thermal Σ∆ modulators ⇒ 10-bit resolution • Bitstream output Sept 2007 ESSCIRC 07 19

Thermal Σ∆ Modulator Spectrum • Thermal LPF f clk = 8kHz ⇒ Noise shaping! • But its finite gain ⇒ Q-noise floor • Off-center chip ⇒ DC offset • Auto-zeroing ⇒ No 1/ f noise Sept 2007 ESSCIRC 07 20

Wind Sensor Performance • After calibration: Speed error: ± 4% Angle error: ± 2° • Same as for original sensor • But, with on-chip electronics • Is being commercialized Sept 2007 ESSCIRC 07 21

Earth’s Magnetic Field X-sensor Sensor Y Sensor • Compass senses at least two components of earth’s field • Field strength < 45µT Goal: Hall-sensor based compass with 1 ° angle error ⇒ Hall-sensor precision < 0.5 µ T ⇒ Precision of readout electronics < 25nV! Sept 2007 ESSCIRC 07 22

Hall Effect + V Hall + I bias - B - V Hall = S H I Bias B Wheatstone bridge model Resistances in bridge model – Are mismatched ⇒ Offset (10mT typical) – Change due to changes in temperature and packaging stress ⇒ Offset drift Sept 2007 ESSCIRC 07 23

Spinning-Current Hall Plate • Bias current rotated, while Hall voltages are summed • Cancels offset due to static bridge mismatch ⇒ 10 - 100µT offset • But thermal settling ⇒ tens of milliseconds per spin cycle ⇒ Time-varying offset e.g. due to temperature and stress remains a problem Sept 2007 ESSCIRC 07 24

Hall Sensor Offset Reduction • Orthogonal coupling – 4 sensors are biased in 4 different directions – Hall voltages are summed ⇒ Instantaneous compensation of time-varying offset • Stable offset < 10µT ⇒ can be trimmed! • Also compensates for errors due to nearby metal objects Sept 2007 ESSCIRC 07 25

Spinning-Current Sensor Output Output (mV) 10 0 Time Offset Signal • Typically 10mV worst case offset • But offset drift < 25nV is required after spinning ⇒ Interface electronics with sub-microvolt offset ⇒ Good linearity over an 80 - 100dB dynamic range Sept 2007 ESSCIRC 07 26

System Architecture Σ∆ V - I Decimation Inst. Counter & Modulator Amp. Summing Spin Hall Slow Fast Fast Digital Sensor Chopper Chopper Chopper Slow Chopper Sub-microvolt offset ⇒ nested chopping • Hall-voltages converted to currents by chopped instrumentation amplifier (fast choppers) • Σ∆ Modulator digitizes resulting currents • Entire front-end is again chopped (slow choppers) • Decimation filter sums and averages Hall-voltages Sept 2007 ESSCIRC 07 27

Chip Micrograph Hall Sensor Inst. Amp. ADC • 0.5 µ m CMOS • Area: 2.9 mm² • Dissipates 21mW (4.2mA @ 5V) • RS232, SPI/ µ wire and PWM interface • Commercial product Timing, Control & Interfaces Sept 2007 ESSCIRC 07 28

Sensor Offset Distribution 6 5 4 3 2 1 0 -3 -2 -1 0 1 2 3 Offset (µT) - 19 Samples Sensor offset (3 σ ) < 4 µ T, but offset drift < 5nT per week! Sept 2007 ESSCIRC 07 29

System Response Measurement Heading error Compass Output 25 2.5 Before calibration 20 X-Vector 2 Offset & Gain calibrated 15 Y-Vector 1.5 Sensor outputs (µT) 10 1 5 0.5 0 0 0 30 60 90 120 150 180 210 240 270 300 330 360 -0.5 0 30 60 90 120 150 180 210 240 270 300 330 360 -5 -10 -1 -1.5 -15 -2 -20 -2.5 -25 Rotation (degrees) • Angle error < 1 ° after calibration and trimming! • State-of-the-art performance! Sept 2007 ESSCIRC 07 30

A Smart Temperature Sensor • Commercial smart temperature sensors are not very accurate ( ± 1.0 ° C from –55 ° C to 125 ° C) • By comparison: class-A Pt100 ± 0.5 ° C • Our goal: ± 0.1 ° C from –55 ° C to 125 ° C with only a single-temperature trim Sept 2007 ESSCIRC 07 31

Operating Principle • substrate PNPs generate: ∆ V BE proportional to absolute temp. (PTAT) V BE complementary to absolute temp. (CTAT) α ⋅ ∆ V V TEMP BE µ = = • ratiometric measurement: + α ⋅ ∆ V V V REF BE BE Sept 2007 ESSCIRC 07 32

Dominant Error Sources • process spread of V BE ⇒ errors of ~3°C • offset in ∆ V BE read-out: 10 µ V ⇒ 0.1°C error • mismatch in 1: p current ratio and gain α : 0.1% ⇒ 0.2°C error Sept 2007 ESSCIRC 07 33

Single-Temperature Calibration • process spread ⇒ PTAT error in V BE • So single-temperature trim is sufficient, provided all other errors are negligible Approach: - reduce all errors except spread to 0.01°C level - correct spread by trimming the bias current Sept 2007 ESSCIRC 07 34