CMOS-oriented EDA Infrastructure Xiang Qiu, Malgorzata - - PowerPoint PPT Presentation

Xiang Qiu, Malgorzata Marek-Sadowska University of California, Santa Barbara Wojciech Maly Carnegie Mellon University

Designing VeSFET-based ICs with CMOS-oriented EDA Infrastructure

Outline

 Introduction  Chain Canvas  Standard cell based physical design flow  Chain Canvas Vs. Basic Canvas  Conclusions

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Introduction

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 Semiconductor markets are dominated by

 ASICs: high NRE cost, high performance, high volume.  FPGAs: low NRE cost, low performance, small volume

 Medium volume?

 VeSFET-based ASICs may fill the gap between ASICs and

• FPGAs. [1][2]

 New technology huge efforts on design automation infrastructure.  Can we re-use CMOS EDA infrastructure for VeSFET- based designs?

 We focus on physical design flow in this talk.

[1] W. Maly, et. al, “Complementary Vertical Slit Field Effect Transistors,” CMU, CSSI Tech-Report , 2008. [2] Y.-W. Lin, M. Marek-Sadowska, W. Maly, A. Pfitzner, and D. Kasprowicz, “Is there always performance overhead for regular canvas?” in Proceedings of ICCD’08, pp. 557-562, 2008.

Vertical Slit Field Effect Transistor

 3D twin-gate transistor[1]

 easy fabrication with SOI-like process

 Excellent electrical characteristics[2]

 huge Ion/Ioff: 1e9  low DIBL: 13mV/V  near ideal subthreshold swing: 65mV/decade  low gate capacitance

r=50nm h=200nm tox=4nm Nsub= 4e17/cm3

[1]. W. Maly, et. al, “Complementary Vertical Slit Field Effect Transistors,” CMU, CSSI Tech-Report , 2008. [2]. W. Maly, et. al, “Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration,” in Proc. of MIXDES’11, pp.145-150, 2011.

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VeSFET Structure[1]

65nm VeSFET

VeSFET based-IC Paradigm

 Regular layout patterns

 Canvases: geometrically identical VeSFETs arrays

 The same radius r and height h

 Circuits are customized by interconnects

 Strictly parallel wires  Diagonal (45- or 135-degree) wires

 Advanced layout style: pillar sharing

A A A A B B B B VDD GND O O O VDD n1 n1

2-input NAND basic canvas 5 shared pillars

Chain Canvases

 Transistors are rotated by 45 degrees  Each pillar is shared by two transistors

 Transistors are chained  2X transistor density

 The same interconnect design rules

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Transistor Isolation

 Some contacted transistors are unwanted.  Isolation

 Physical  Electrical

 Apply cut-off voltage  Short drain and source

 Wasted area!

7 A 1 2 B 3 4 T1 T2 X/X 3 2 Tp

DP X X B A B A 1 1 1

T1 T2 Tp A A B B X X 1 2 3

4

A A B B 1 2 3

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Static CMOS-like Standard Cell Generation

 CMOS-like layout patterns

 aligned gate pillars connected by wires  aligned poly gates  shared drain/source pillars  diffusion abutment

 CMOS cell generation algorithms can be reused.

8 A B O gnd vdd A A A B B B O O vdd vdd gnd gnd gnd gnd vdd vdd vdd 2-input NAND

Static CMOS-like Standard Cell Generation

 Transistor isolation  Diffusion break  Sizing by transistor duplication

 Transistor size

=> effective transistor density

 Vs. Basic Canvas cells

 easier cell generation  shorter wires

CMOS diffusion break VeSFET transistor isolation A B O O vdd vdd gnd A B O gnd A B A B O vdd vdd A B vdd vdd vdd gnd gnd gnd 9 2-input NANDX2

 Similar to CMOS standard cell placement.  Neighboring rows share power/ground lines.  Power/ground lines are also for transistor isolation.

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Row-based Standard Cell Placement

N/FN S/FS shared power line shared ground line shared ground line

Inter-cell Routing

 Two disjoint routing grids

 Vias aligned with pillars: D/S pillars cannot connect to G pillars

by only H/V wires

 Jumper wires: diagonal wires bridging D/S- and G-grids.

 Most inter-cell nets have both D/S pins and G pins.

 Routing each single net

• n both grids may need

multi layers of jumper wires

 Route each net on only

• ne grid, only one layer
• f jumper wires

 Greedy net partitioning

 Balance routing demands  Balance pin density.

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Jumper wires

Cell Level Comparison

 Design INV, BUF, NAND2, NOR2, AOI21, OAI21 on both canvases  Design 1X, 2X, 4X cells for each logic  More pillar sharing  more area saving

 Greater gate size  More gate inputs

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CELL Basic Canvas Chain Canvas 1X 2X 4X 1X 2X 4X INV 8 16 32 12 18 30 BUF 16 32 64 18 30 54 NAND2 16 32 64 18 30 54 NOR2 16 32 64 18 30 54 AOI21 24 48 96 24 40 72 OAI21 24 48 96 24 40 72 AVG 1 1 1 1.15 0.93 0.83

Table 1. # of pillars occupied by cells mapped on BC and CC

Cell Level Comparison (Cont.)

 Chain canvas

 shorter wires  fewer vias  gate size , improvement

0.2 0.4 0.6 0.8 1 1.2 1X 2X 4X basic canvas chain canvas Average intra-cell wire length 0.2 0.4 0.6 0.8 1 1.2 1X 2X 4X basic canvas chain canvas Average intra-cell via count 13

Cell Level Comparison (Cont.)

 Performance and power comparison

 Smaller parasitic RC for CC-based cells.  Determine the frequency and power delay product (PDP) of a 5-

stage ring oscillator.

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1X 2X 4X basic canvas chain canvas Average RO frequency Average RO PDP 0.2 0.4 0.6 0.8 1 1.2 1X 2X 4X basic canvas chain canvas 14

Circuit Level Comparison

 LGSynth91 benchmarks with thousands of gates

 Mapped with a library of 6 1X cells(INV, BUF, NAND2, NOR2,

AOI21, OAI21).

 CC-G: G-grid only routing  CC-G/DS: nets evenly spread on both grids.

0.6 0.7 0.8 0.9 1 1.1 1.2 area wire length # VIAs BC CC-G CC-G/DS 1 2 3 4 5 6 7 8 # metal layers 15

Circuit Level Comparison (Cont.)

 Static timing analysis

 non-linear delay model for each cell.  parasitic inter-cell interconnect RC extracted by Star-RC.

 Power estimation

 Total interconnect capacitance

0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 longest path delay total interconnect capacitance BC CC-G CC-G/DS 16

Conclusions

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 We propose chain canvases,

 CMOS ASIC EDA infrastructure re-usable.  2X transistor density.  Transistor isolation reduces transistor utilization.  Transistor utilization improves as gate size increases.

 Chain canvases Vs. Basic Canvases

 Easier cell generation  better routability  smaller parasitic capacitance  better performance  lower power consumption  slightly greater footprint area using unit size gates

Q & A

Thank you!

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