Design and calibration of System-on-Chip switched capacitor array - - PowerPoint PPT Presentation

Design and calibration of System-on-Chip switched capacitor array based waveform digitizers for particle tracking

Isar Mostafanezhad, Ph.D. Founder and CEO, Nalu Scientific, LLC Sep 14, 2018

1 On behalf of teams at Nalu Scientific and University of Hawaii Work sponsored by DOE Office of Science SBIR program

2800 Woodlawn Dr. Ste #240 Honolulu, HI 96822 info@naluscientific.com +1 (888) 717-6484

About Nalu Scientific

2

Photo: http://www.myhawaiirealestateonline.com/manoa-real-estate/

Mission statement: Design house for DOE electronics needs with commercial grade support

ASIC Design Mixed signal System-on-Chip Power optimization Full suite commercial grade Cadence license and server + design kits Hardware Design FPGA, VHDL development Implementation Bring up and debugging Complex multi-layer boards Expertise in: Radiation detection, fast timing, time of flight measurements Readout electronics for HEP/NP

• 1. Various Front-end Chip:
• Event based digitizer+DSP
• 4-32 channel scope on chip
• 1-15 Gsa/s, 12 bit res.
• Low SWaP
• Low cost
• User friendly

Main application: Particle collider experiments (Belle II at KEK in Japan)

• 3. Other applications:
• Lidar
• UAV radar
• PET imaging
• Low light detection
• Picosecond timing

Waveform Digitizer SoCs for Single Photon Time of Fight Detection: Compact, Low Cost, Low Power

NALU SCIENTIFIC, LLC

• 2. Integration:
• SiPM
• PMT
• LAPPD
• Antenna arrays

A Bit of History: Belle II Upgrade

4

2015 2018 Belle II: e+ e- experiment at 40x luminosity of Belle -> Detector needs to operate at severe beam background

Belle II: KLM Scintillator Upgrade 20k+ channels at 1 GSa/s ea.

KLM detectors:

• Endcap: scintillators
• Barrel: scintillators +RPCs

Located outside the magnet

5

Belle II Summer School, PNNL, August 2015

Belle II: KLM Scintillator Upgrade 20k+ channels at 1 GSa/s + DSP

6

Barcode Laser engraving 1 2 3 4 Benchtop testing Crate testing at UH

1) KLM Motherboard 2) KLM Ribbon Header Interface Card (RHIC) 3) KLM SCROD Rev A 4) TARGETX Daughtercards

Electronics testing

7

NALU SCIENTIFIC, LLC---- PREPARED FOR NASA, AUG 7, 2017- DO NOT PUBLISH

KLM final packaging: 111 modules in 4 large crates ~16k channels

Motherboards and RHICs staged in minicrates Minicrates inserted in large crates Crates closed and ready for truck

8

NALU SCIENTIFIC, LLC---- PREPARED FOR NASA, AUG 7, 2017- DO NOT PUBLISH

TOP and KLM Subdetectors fully commissioned

9

2017 IEEE NSS-MIC, N-05 — Analog and Digital Circuit I Nalu Scientific, LLC

Lessons learned 1: Classical HEP/NP Experiment

10

2017 IEEE NSS-MIC, N-05 — Analog and Digital Circuit I Nalu Scientific, LLC

Lessons learned 2: Opportunities

HEP/NP electronics need to be:

• Rad hard
• High performance
• Low cost
• Low power
• Highly integrated
• User friendly

Optimize to get to sweet spot = 2-3x gain Solution: new design/SoC integration = 10 x gain

11

Low cost High performance Low power

How to save power? - Analog Memory

12

• Always sampling
• On-demand digitizing

Gary Varner

Benefits of Higher Integration - SoC

• Analog memory:
• Sampling always on (1-10 Gsa/s), but at low power
• Digitize only Region of Interest (ROI)
• Long analog buffer -> suitable for large experiments
• Digital processing:
• Per channel cost reduction by a factor of 4
• Relax thermal design by 40% reduction in power dissipation
• Trigger time-stamping at the front-end
• Eliminating the need for costly high-end FPGAs
• User friendly: substantially reducing the FPGA firmware development labor
• Reduced complexity and design and cabling effort/cost for the front-end boards

13

Analog/Mixed signal design Digital/Synthesized logic System-on-Chip (SoC)

SBIR Data Rights.

SBIR Project: ASoC- System on Chip

Compact, high performance waveform sampling- Funded Phase II

14

Spec Sampling rate 2-4 Gsa/s ABW 0.9-1.5GHz Depth 32k Sa N channels: 4-8 Fab 250nm CMOS

Key Contribution:

• High performance digitizer: 3+ Gsa/s
• Highly integrated
• Commercially available
• 5mm x 5mm die size

Waveform Sampling Core Funded DOE Phase II Project

Nalu Scientific- ASIC developments

NALU SCIENTIFIC, LLC-

All chips, are designed with commercial grade tools and licenses and can be sold once commercialized.

ASoC Under test

15

ASoC Evaluation FMC Card

ASoC Test/Calibration Underway

• Digitized waveform vs. ideal sinewave
• Calculating residuals and calibrating ADC

bias points for optimal performance

16

68.5V SiPM bias - self triggered Temporal ROI readout

ASoC Next steps

• Wrap up testing and publish results
• Send evaluation modules to collaborators for taking data and testing (aka sales!)
• Prepare for next tape-out:
• Funded SBIR Phase II
• Address minor bugs
• More integration/features:
• Internal developments on applications of ASoC

17

AARDVARC Rev.1 Packaged (QFN-12mmx12mm) AARDVARC Rev.1 Die wire-bonded to pins AARDVARC Rev.1 Input stage wire-bonds http://www.naluscientific.com/

Moving toward higher sample rate: AARDVARC : 5-15 GSa/s Digitizer System-on-Chip – Phase II SBIR

Main focus: 5-10ps timing resolution

19

AARDVARC Eval PCB semi populated. Testing ongoing. So far NO SMOKE!

Current SoC-ASIC Projects

Project Sampling Frequency (GHz) Input BW (GHz) Buffer Length (Samples) Number of Channels Timing Resolution (ps) Integratio n Built-in Readout Available Date ASoC 3-5 0.8 32k 8 35 SoC Pre amps Parallel Aug 2018 SiREAD 1-3 0.7 4k 64 80-120 SoC Amp, bias Fast serial May 2018 AARDVARC 6-10 2.5 32k 4-8 4-8 SoC Pre amps Fast serial Sep 2018

20

• ASoC: Analog to digital converter System-on-Chip
• Rev 1 under test – Eval card available
• SiREAD: SiPM specialized readout chip with bias and control
• Rev 1 under test
• AARDVARC: Variable rate readout chip for fast timing and low deadtime
• Rev 1 under test –

All chips, are designed with commercial grade tools and licenses and can be sold once commercialized.

NALU SCIENTIFIC, LLC-

Seeking Collaborations

• R&D funding has been secured for :
• 3x SBIR Phase I
• 2x SBIR Phase II
• Enabling technology:
• Low cost ($10s/ch - $100s/ch)
• High precision (100-5 ps)
• Compact (SoC)
• Low power (20-50 mW/ch)
• Long analog buffer (3-10us/ch)
• Looking to develop the next generation instruments for:
• Fast diagnostics imaging
• High channel count, low cost Time of Flight (ToF)
• Radiation detection

21

NALU SCIENTIFIC, LLC