Design and calibration of System-on-Chip switched capacitor array - PowerPoint PPT Presentation

Design and calibration of System-on-Chip switched capacitor array based waveform digitizers for particle tracking Isar Mostafanezhad, Ph.D. Founder and CEO, Nalu Scientific, LLC Sep 14, 2018 2800 Woodlawn Dr. Ste #240 Honolulu, HI 96822 On behalf of teams at Nalu Scientific and University of Hawaii info@naluscientific.com Work sponsored by DOE Office of Science SBIR program +1 (888) 717-6484 1

About Nalu Scientific ASIC Design Mixed signal System-on-Chip Power optimization Full suite commercial grade Cadence license and server + design kits Hardware Design FPGA, VHDL development Implementation Bring up and debugging Complex multi-layer boards Photo: http://www.myhawaiirealestateonline.com/manoa-real-estate/ Expertise in: Mission statement: Radiation detection, fast timing, time of flight measurements Design house for DOE electronics needs with Readout electronics for HEP/NP commercial grade support 2

Waveform Digitizer SoCs for Single Photon Time of Fight Detection: Compact, Low Cost, Low Power Main application: Particle collider experiments (Belle II at KEK in Japan) 1. Various Front-end Chip: 2. Integration: • SiPM • Event based digitizer+DSP • PMT 3. Other applications: • 4-32 channel scope on chip • LAPPD • Lidar • 1-15 Gsa/s, 12 bit res. • Antenna arrays • UAV radar • Low SWaP • PET imaging • Low cost • Low light detection • User friendly • Picosecond timing NALU SCIENTIFIC, LLC

A Bit of History: Belle II Upgrade 2015 2018 Belle II: e+ e- experiment at 40x luminosity of Belle -> Detector needs to operate at severe beam background 4

Belle II: KLM Scintillator Upgrade 20k+ channels at 1 GSa/s ea. KLM detectors: ◦ Endcap: scintillators ◦ Barrel: scintillators +RPCs Located outside the magnet Belle II Summer School, PNNL, August 2015 5

Belle II: KLM Scintillator Upgrade 20k+ channels at 1 GSa/s + DSP 1) KLM Motherboard 2) KLM Ribbon Header 3 Interface Card (RHIC) 3) KLM SCROD Rev A 4) TARGETX Daughtercards 2 1 Benchtop testing 4 Crate testing at UH Barcode Laser engraving 6

Electronics testing 7 NALU SCIENTIFIC, LLC---- PREPARED FOR NASA, AUG 7, 2017- DO NOT PUBLISH

KLM final packaging: 111 modules in 4 large crates ~16k channels Crates closed and ready for truck Motherboards and Minicrates inserted in large crates 8 RHICs staged in minicrates NALU SCIENTIFIC, LLC---- PREPARED FOR NASA, AUG 7, 2017- DO NOT PUBLISH

TOP and KLM Subdetectors fully commissioned 2017 IEEE NSS-MIC, N-05 — Analog and Digital Circuit I Nalu Scientific, LLC 9

Lessons learned 1: Classical HEP/NP Experiment 2017 IEEE NSS-MIC, N-05 — Analog and Digital Circuit I Nalu Scientific, LLC 10

Lessons learned 2: Opportunities HEP/NP electronics need to be: ◦ Rad hard Low cost ◦ High performance ◦ Low cost ◦ Low power ◦ Highly integrated ◦ User friendly Optimize to get to sweet spot = 2-3x gain Low power High performance Solution: new design/SoC integration = 10 x gain 11

How to save power? - Analog Memory • Always sampling • On-demand digitizing Gary Varner 12

Benefits of Higher Integration - SoC • Analog memory: • Sampling always on (1-10 Gsa/s), but at low power Analog/Mixed signal design • Digitize only Region of Interest (ROI) • Long analog buffer -> suitable for large experiments • Digital processing: • Per channel cost reduction by a factor of 4 • Relax thermal design by 40% reduction in power dissipation • Trigger time-stamping at the front-end Digital/Synthesized logic • Eliminating the need for costly high-end FPGAs • User friendly: substantially reducing the FPGA firmware development labor • Reduced complexity and design and cabling effort/cost for the front-end boards System-on-Chip (SoC) SBIR Data Rights. 13

SBIR Project: ASoC- System on Chip Compact, high performance waveform sampling- Funded Phase II Spec Sampling rate 2-4 Gsa/s Waveform Sampling Core ABW 0.9-1.5GHz Depth 32k Sa N channels: 4-8 Fab 250nm CMOS Key Contribution: • High performance digitizer: 3+ Gsa/s • Highly integrated • Commercially available • 5mm x 5mm die size Funded DOE Phase II Project All chips, are designed with commercial grade tools and licenses and can be sold once commercialized. Nalu Scientific- ASIC developments 14 NALU SCIENTIFIC, LLC-

ASoC Under test ASoC Evaluation FMC Card 15

ASoC Test/Calibration Underway • Digitized waveform vs. ideal sinewave • Calculating residuals and calibrating ADC bias points for optimal performance 68.5V SiPM bias - self triggered Temporal ROI readout 16

ASoC Next steps • Wrap up testing and publish results • Send evaluation modules to collaborators for taking data and testing (aka sales!) • Prepare for next tape-out: • Funded SBIR Phase II • Address minor bugs • More integration/features: • Internal developments on applications of ASoC 17

Moving toward higher sample rate: AARDVARC : 5-15 GSa/s Digitizer System-on-Chip – Phase II SBIR AARDVARC Rev.1 AARDVARC Rev.1 AARDVARC Rev.1 Packaged (QFN-12mmx12mm) Die wire-bonded to pins Input stage wire-bonds Main focus: 5-10ps timing resolution http://www.naluscientific.com/

AARDVARC Eval PCB semi populated. Testing ongoing. So far NO SMOKE! 19

Current SoC-ASIC Projects Project Sampling Input Buffer Length Number of Timing Integratio Built-in Readout Available Frequency BW (Samples) Channels Resolution n Date (GHz) (GHz) (ps) ASoC 3-5 0.8 32k 8 35 SoC Pre amps Parallel Aug 2018 SiREAD 1-3 0.7 4k 64 80-120 SoC Amp, bias Fast serial May 2018 AARDVARC 6-10 2.5 32k 4-8 4-8 SoC Pre amps Fast serial Sep 2018 • ASoC : Analog to digital converter System-on-Chip • Rev 1 under test – Eval card available • SiREAD : SiPM specialized readout chip with bias and control • Rev 1 under test • AARDVARC : Variable rate readout chip for fast timing and low deadtime • Rev 1 under test – All chips, are designed with commercial grade tools and licenses and can be sold once commercialized. 20 NALU SCIENTIFIC, LLC-

Seeking Collaborations • R&D funding has been secured for : • 3x SBIR Phase I • 2x SBIR Phase II • Enabling technology: • Low cost ($10s/ch - $100s/ch) • High precision (100-5 ps) • Compact (SoC) • Low power (20-50 mW/ch) • Long analog buffer (3-10us/ch) • Looking to develop the next generation instruments for: • Fast diagnostics imaging • High channel count, low cost Time of Flight (ToF) • Radiation detection 21 NALU SCIENTIFIC, LLC