Dariusz Makowski Department of Microelectronics and Computer - - PowerPoint PPT Presentation
Embedded Systems Dariusz Makowski Department of Microelectronics and Computer Science tel. 631 2720 dmakow@dmcs.pl http://fiona.dmcs.pl/es 1 Department of Microelectronics and Computer Science Embedded Systems Lecture Agenda Agenda
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Electronic or mechanic device used for storing digital data or computer programs (operating system and applications).
Electronic device connected to processor via system bus or computer interface. External devices are used to realise dedicated functionality of the computer system. Internal devices are mainly used by processor and operating system.
Electrical connection or subsystem that transfers data between computer components: processors, memories and peripheral devices. System bus is composed of dozens of multiple connections (Parallel Bus) or a few single serial channels (Serial Bus).
Electronic or optical device that allows to connect two or more devices. Interface can be parallel or serial.
Department of Microelectronics and Computer Science Embedded Systems
Universal Serial Asynchronous Receiver-Transmitter (USART), Serial Peripheral Interface (SPI), Synchronous Serial Controller (SSC) I2C, Two-wire Interface (TWI), Controlled Area Network (CAN), Universal Serial Bus (USB), Ethernet 10/100 Mbits (1 Gbit), Debug/programming interface (EIA RS232, JTAG, SPI, DBGU).
Department of Microelectronics and Computer Science Embedded Systems
Debug interface (DBGU), Universal Serial Asynchronous Receiver-Transmitter (USART), Serial Peripheral Interface (SPI), Synchronous Serial Controller (SSC), I2C, Two-wire Interface (TWI), Controlled Area Network (CAN), Universal Serial Bus (USB, host, endpoint), Ethernet 10/100 Mbits, Programming interface (JTAG).
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
D0-D7 D0-D7 Clk Clk
Department of Microelectronics and Computer Science Embedded Systems
Mark Space
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Transmitter
Internal clock
Transmitter Receiver Receiver
Data Clock
Internal clock
Similar reference frequency
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
DTE Data Terminal Equipment – terminal, PC DCE - Data Circuit-terminating Equipment – Modem DSR - Data Set Ready - modem DTR - Data Terminal Ready – terminal RTS - Request to Send Data CTS - Clear to Send - ready to send data
Remarks Symbol Start transmission Line state Modem ready Circuit Request to send Ready to send Computer ready
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
(http://www.elester-pkp.com.pl/index.php?id=92&lang=pl&zoom=0)
Department of Microelectronics and Computer Science Embedded Systems
(chapter 30)
Department of Microelectronics and Computer Science Embedded Systems
Asynchronous data transmission compatible with RS232 standard (8 bits, single parity bit – can be switched off), Single system interrupt, shared with PIT, RTT, WDT,DMA, PMC, RSTC, MC, Frame correctness analysis, RxD buffer overflow signal, Diagnostic modes: external loopback, local loopback and echo, Maximum transmission baudrate 1 Mbit/s, Direct connectivity to debug module buildin ARM core (COMMRx/COMMTx).
Department of Microelectronics and Computer Science Embedded Systems
Interrupt signal Input-Output ports Serial Transceiver
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Receiver Buffer Overflow (BGU_RHR) Parity Error (PE) Frame Error (FE)
Department of Microelectronics and Computer Science Embedded Systems
static void Open_DBGU (void){
AT91C_BASE_PIOC->PIO_PDR)
AT91C_US_CHMODE_NORMAL, AT91C_US_PAR_NONE)
}
Department of Microelectronics and Computer Science Embedded Systems
Interrupts are disabled. void dbgu_print_ascii (const char *Buffer) { while ( data_are_in_buffer ) { while ( …TXRDY... ){}; /* wait intil Tx buffer busy – check TXRDY flag */ DBGU_THR = ... /* write a single char to Transmitter Holding Register */ } } void dbgu_read_ascii (const char *Buffer, unsigned int Size){ do { While ( ...RXRDY... ){}; /* wait until data available */ Buffer[...] = DBGU_RHR; /* read data from Receiver Holding Register */ } while ( …read_enough_data... ) }
Department of Microelectronics and Computer Science Embedded Systems
(rozdział 34)
Department of Microelectronics and Computer Science Embedded Systems
Features of Universal Synch. Asynch. Receiver-Transmitter:
Asynchronous or synchronous data transfer, Programmable frame length, parity, stop bits, Single system interrupt (shared with: PIT, RTT, WDT,DMA, PMC, RSTC, MC), Analysis of correctness of received frames, Buffer overflow error TxD or RxD, Elastic buffer – possibility of receiving frames with different length (uses additional counter), Diagnostic modes: external loopback, local loopback and echo, Maximum transmission speed 1 Mbit/s, Hardware flow control, Support for Multidrop transmission – data and address, Available Direct Memory Access channel, Support for RS485 differential transmission mode and infrared systems (build-in IrDA modulator-demodulator).
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Master Output Slave Input Master Input Slave Output
CS
Department of Microelectronics and Computer Science Embedded Systems
Clock signal configuration: Clock polarisation: Negative CPOL = 0 (low level, 8 clock signals), Positive CPOL = 1 (high level, 8 clock signals), Clock phase: Zero clock phase (data sampled on first clock slope), Delayed clock phase (data sampled on second clock slope).
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
I²C standard is applied to various digital and analogue devices: PCF8563/8583 – clock, calendar, alarm, timer and NVRAM, PCF8574 – 8-bit IO expander, PCF8576, PCF8577 – LCD controllers, PCF8582 - EEPROM memory, 256 bajts (1, 2, 4 kB, ... MB), PCF8591 - 8-bit, 4-channels ADC/DAC converter.
Department of Microelectronics and Computer Science Embedded Systems
Master device – initialize transmission, generates clock signal Slave device – analyse signals on bus, read address and data
Department of Microelectronics and Computer Science Embedded Systems
Transmission start – START signal (falling slope on SDA, change from “1” to “0”, during valid clock signal, SCL = ”1”). Signal generated by Master. Transmission end – STOP (rising edge on SDA bus, change from “0” to “1” during valid clock signal, SCL = ”1”). Signal generated by Master.
Department of Microelectronics and Computer Science Embedded Systems
A) Transmission initialised by Master, START condition. B) Transmission of 8 bits (7 address bits, 1 R/W bit). C) After 8 bit (clk signals) SDA bus is controlled by Slave (9th clk). Acknowledge is generated to confirm address receive ACK = '0' or not (ACK = “1”). E) Data read or write phase – Master or Slave sends 8 data bits. F) Transmission is finished when ACK signal is generated by data receiver (Master or Slave). Master generates Stop condition.
Department of Microelectronics and Computer Science Embedded Systems
7-bit 7-bit
Department of Microelectronics and Computer Science Embedded Systems
ARM processors are equipped with TWI interface compatible with developed by Philips I2C (I2C interface was patented by Philips).
Compatible with I2C, Master, Multimaster or Slave modes, IO voltage equal to 3,3 V, Maximum transmission speed: 400 kHz, Transfers triggered with interrupts, Automatically Slave mode activated when collision detected on I2C bus (Arbitration-lost interrupt), Interrupt triggered when I2C slave address recognised, Automatic bus busy recognition, Support for 7 and 10-bits addresses.
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Build-in thermometer -55 – 125 C, Thermometer resolution: 9 bits, Thermometer accuracy +/- 2 C, Thermostat mode, 32 bytes of SRAM, Power Supply 2,2 – 5,5 V, Interface compatible with I2C (400 kHz).
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
1 kbps 10 kbps 100 kbps 1 Mbps 10 Mbps 100 Mbps 1 cm 10 cm 1 m 10 m 100 m
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Asynchronous, serial, differential data transmission, Automatic recognition of connected/disconnected devices, automatic configuration, Single, standardized connector, Up to 127 devices on single bus, Automatic detection and errors correction, Transmission speed: LOW 1.5 Mb/s, specification USB >1.1, FULL 12 Mb/s, specification USB >1.1, HIGH 480 Mb/s, specification USB 2.0, Specification USB 3.0 => 5 Gb/s.
Department of Microelectronics and Computer Science Embedded Systems
USB is designed as a star bus. USB model is composed of three layers: Physial layer, Logical layer, Functional layer.
Data pipe Control pipe Signal wires USB interface USB interface Application USB driver Logical device Device function
Department of Microelectronics and Computer Science Embedded Systems
Virtual channels (Pipes) Control channel (EP0) Data channels EP1 – EP30 (End Points)
Department of Microelectronics and Computer Science Embedded Systems
USB “A” and “B” type Mini USB Differential transmission, half-duplex. Included power supply bus 5 V/500 mA
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Enumeration – configuration of devices connected to USB bus after connection to disconnection of devices from bus. Enumeration is performed by Master node (address 0). Master assigned individual address to devices connected to USB and configures basic parameters: Device address in USB area, Transfer mode, Transfer direction (read, write, read-write), Size of data packet, Transmission speed, Allocates buffers for virtual channels, Allocated power for connected devices.
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Features of USB module of HC908: Interface compatible with USB 2.0 full speed, 12 Mbps data rate, Build-in 3.3 V regulator, Endpoint 0 with 8-bytes Tx/Rx buffers 64 bytes buffer for endpoints 1-4.
Department of Microelectronics and Computer Science Embedded Systems
Compatible with USB 2.0–USB-IF high speed, Based on 8051 core, Integrated 16 kB RAM (SRAM) Memory can be loaded from USB, Memory can be loaded from external EEPROM. Four programmable endpoints (BULK/INTERRUPT/ISOCHRONOUS) Additional 64 bytes endpoint (BULK/INTERRUPT), Parallel 8- or 16-bits external interface, DMA channel, GPIF (General Programmable Interface)
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems
Department of Microelectronics and Computer Science Embedded Systems