Comparison of Channel Protocols for Fast, Low Energy Communication - - PowerPoint PPT Presentation

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Comparison of Channel Protocols for Fast, Low Energy Communication - - PowerPoint PPT Presentation

Comparison of Channel Protocols for Fast, Low Energy Communication over Transmission Lines Shomit Das*, Kenneth S. Stevens The University of Utah *now with AMD Research Exascale Challenges Cost of data movement relative to cost of a flop*


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Comparison of Channel Protocols for Fast, Low Energy Communication over Transmission Lines

Shomit Das*, Kenneth S. Stevens The University of Utah

*now with AMD Research

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Exascale Challenges

Cost of data movement relative to cost of a flop* Data movement energy component** *

  • J. Shalf et.al., Exascale Computing Technology Challenges, LNCS 2011

** G. Kestor et.al., Quantifying the energy cost of data movement in scientific applications, IISWC 2013

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Interconnect Challenges

*Shekhar Borkar, Exascale Computing- Fact or Fiction? IPDPS 2013

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Global Interconnect

Exascale System Architecture Examples (proposed) AMD NVidia

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Transmission Lines

On-chip Transmission Lines Repeated RC wire SerDes based TL interconnect Transmission Lines require thick top level metals They require carefully designed signal and return paths Signal integrity depends on interconnect aspect ratio among many other factors Bandwidth per unit area suffers as a result Analog signaling techniques such as differential signaling, current mode signaling are applied Higher frequencies can be used SerDes means more timing and energy considerations

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Transmission Lines – Design and Simulation

Transmission Line Interconnect Design Environment *H.G. Rhew et.al., A 22Gb/s, 10 mm on-chip serial link over lossy Transmission Line, ESSCIRC 2012

7mm TL

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Communication Protocols

Dual Rail Bundled Data 4-phase Bundled Data 2-phase Source Asynchronous Signaling Clocked latched Clocked flopped Source Synchronous

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Communication Protocols - SAS

Source Asynchronous Signaling (uncoupling req and ack)

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Metrics

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Models – Cycle Time

Cycle Time expressions

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Models – Latency

Latency expressions

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Models – Energy

Energy per transaction expressions

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Comparisons – Cycle Time

5 10 15 20 25 30 35 40 45 50 DualRail BD4 BD2 SAS Clock_l Clock_f SrcSync

Cycle Time Comparison

10 20 30 40 50 60 70 80 90 100 DualRail BD4 BD2 SAS Clock_l Clock_f SrcSync

RC vs TL

RC TL

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Comparisons - Latency

1 2 3 4 5 6 7 8 9 10 DualRail BD4 BD2 SAS Clock_l Clock_f SrcSync

Latency Comparison

5 10 15 20 25 DualRail BD4 BD2 SAS Clock_l Clock_f SrcSync

RC vs TL

RC TL

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Comparisons - Energy

20 40 60 80 100 120 140 160 180 200 DualRail BD4 BD2 SAS Clock_l Clock_f SrcSync

Energy Comparison

100 200 300 400 500 600 700 800 DualRail BD4 BD2 SAS Clock_l Clock_f SrcSync

RC vs TL

RC TL

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Key Observations

20 40 60 80 100 120 DualRail BD4 BD2 SAS Clock_l Clock_f SrcSync

Percentage difference in Cycle Time

TL RC

  • Clocked protocols have better timing

characteristics

  • Clock distribution energy is a killer
  • Single “cycle” communication due to

discontinuity-free requirement of TLs

  • SAS provides clocked-like timing without the

energy overhead of clock distribution

  • Longer distances more “manageable” using

Transmission Lines

  • SAS outperforms other protocols in almost all

metrics

  • No wavepipelining
  • SAS robust to variation due to decoupled

throughput and wire latency Effect of link length (7mm vs 3mm)