CSE 140 Lecture 11 Standard Combinational Modules CK Cheng and Diba - - PowerPoint PPT Presentation

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CSE 140 Lecture 11 Standard Combinational Modules CK Cheng and Diba - - PowerPoint PPT Presentation

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CSE 140 Lecture 11 Standard Combinational Modules CK Cheng and Diba Mirza CSE Dept. UC San Diego 1 Part III - Standard Combinational Modules (Harris: 2.8, 5) Signal Transport Decoder: Decode address Encoder: Encode address

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CSE 140 Lecture 11 Standard Combinational Modules

CK Cheng and Diba Mirza CSE Dept. UC San Diego

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Part III - Standard Combinational Modules (Harris: 2.8, 5)

Signal Transport

  • Decoder: Decode address
  • Encoder: Encode address
  • Multiplexer (Mux): Select data by address
  • Demultiplexier (DeMux): Direct data by address
  • Shifter: Shift bit location

Data Operator

  • Adder: Add two binary numbers
  • Multiplier: Multiply two binary numbers
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  • 1. Decoder
  • Definition
  • Logic Diagram
  • Application (Universal Set)
  • Tree of Decoders
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iClicker: Decoder Definition

  • A. A device that decodes
  • B. An electronic device that converts signals

from one form to another

  • C. A machine that converts a coded text into
  • rdinary language
  • D. A device or program that translates

encoded data into its original format

  • E. All of the above

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Decoder Definition: A digital module that converts a binary address to the assertion of the addressed device

y0 y1 y7

I0 I1 I2 1 2

1 2 3 4 5 6 7

E (enable) n inputs n= 3 2n outputs 23= 8

yi = 1 if E= 1 & (I2, I1, I0 ) = i yi= 0 otherwise

n to 2n decoder function:

. .

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Interconnect: Decoder, Encoder, Mux, DeMux

Processors Decoder: Decode the address to assert the addressed device Mux: Select the inputs according to the index addressed by the control signals P1 Memory Bank

Mux

P2 Pk

Demux

Decoder

Mux

Data Address

Address k Address 2 Address 1 Data 1 Data k

Arbiter n n-m m 2m

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PI Q: What is the output Y3:0 of the 2:4 decoder for (A1, A0) = (1,0)?

  • A. (1, 1, 0, 0 )
  • B. (1, 0, 1, 1)
  • C. (0, 0, 1, 0)
  • D. (0, 1, 0, 0)
  • 1. Decoder: Definition

2:4 Decoder A1 A0 Y3 Y2 Y1 Y0 00 01 10 11 1 1 1 1 1 Y3 Y2 Y1 Y0 A0 A1 1 1 1

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  • N inputs, 2N outputs
  • One-hot outputs: only one output HIGH at once
  • 1. Decoder: Definition

2:4 Decoder A1 A0 Y3 Y2 Y1 Y0 00 01 10 11 1 1 1 1 1 Y3 Y2 Y1 Y0 A0 A1 1 1 1

E E= 1

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Decoder: Logic Diagram

y0 I2’ I1’ I0’ y1 I2 I1’ I0’ E y7 I2 I1 I0 . .

Output Expression: yi = E·mi y0=1 if E=1 & (I2, I1, I0)=(0,0,0) y7=1 if E=1 & (I2, I1, I0)=(1,1,1)

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Decoder Application: universal set {Decoder, OR}

Example: Implement the following functions with a 3-input decoder and OR gates. i) f1(a,b,c) = Σm(1,2,4) ii) f2(a,b,c) = Σm(2,3), iii) f3(a,b,c) = Σm(0,5,6)

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Decoder Application: universal set {Decoder, OR}

Example: Implement functions i) f1(a,b,c) = Σm(1,2,4) ii) f2(a,b,c) = Σm(2,3), iii) f3(a,b,c) = Σm(0,5,6) with a 3-input decoder and OR gates.

I0

y0 y1 . . y7

c b a I1 I2

1 2 3 4 5 6 7

E=1 y1 y2 y4 f1 y2 y3 f2 y0 y6 f3 y5

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  • OR minterms

Decoders

2:4 Decoder A B 00 01 10 11 Y = AB + AB Y AB AB AB AB Minterm = A ⊕ B

E=1

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Tree of Decoders

Implement a 4-24 decoder with 3-23 decoders.

I0

y0 y1 y7

I1 I2

1 2 3 4 5 6 7

I0

y8 y9 y15

I1 I2

1 2 3 4 5 6 7

a d c b

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Implement a 6-26 decoder with 3-23 decoders.

E D0 I2, I1, I0 D1

y0 y7 y8 y15

D7

y56 y63

E I2, I1, I0 I2, I1, I0 I5, I4, I3

Tree of Decoders

… …

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PI Q: A four variable switching function f(a,b,c,d) can be implemented using which of the following?

  • A. 1:2 decoders and OR gates
  • B. 2:4 decoders and OR gates
  • C. 3:8 decoders and OR gates
  • D. None of the above
  • E. All of the above

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  • 2. Encoder
  • Definition (What is it?)
  • Logic Diagram (How is it realized?)
  • Priority Encoder (Special type of encoder)
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iClicker: Definition of Encoder

  • A. Any program, circuit or algorithm which encodes
  • B. In digital audio technology, an encoder is a

program that converts an audio WAV file into an MP3 file

  • C. A device that convert a message from plain text

into code

  • D. A circuit that is used to convert between digital

video and analog video

  • E. All of the above

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  • 2. Encoder: Definition

At most one Ii = 1. (yn-1,.., y0 ) = i if Ii = 1 & En = 1 (yn-1,.., y0 ) = 0 otherwise. A = 1 if En = 1 and one i s.t. Ii = 1 A = 0 otherwise. 8 inputs 3 outputs

y0 y1 y2

1 2 3 4 5 6 7

En A

I0 I7

1 2

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Encoder Definition: A digital module that converts the assertion of a device to the binary address of the device.

yn-1 …y0 E A I2n-1…I0 8 inputs 3 outputs

y0 y1 y2

1 2 3 4 5 6 7

E At most one Ii = 1. (yn-1,.., y0 ) = i if Ii = 1 & E = 1 (yn-1,.., y0 ) = 0 otherwise. A = 1 if E = 1 and one i s.t. Ii = 1 A = 0 otherwise.

Encoder Description:

A

I0 I7

1 2

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Encoder: Logic Diagram

En I1 I3 I5 I7 y0 En I2 I3 I6 I7 y1 En I4 I5 I6 I7 y2 En I0 I1 I6 I7 A . .

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Priority Encoder:

1 2 3

E Eo Gs

I0 I3

y0 y1 1

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Priority Encoder: Definition

Description: Input (I2n-1,…, I0), Output (yn-1 ,…,,y0) (yn-1 ,…,,y0) = i if Ii = 1 & E = 1 & Ik = 0 for all k > i (high bit priority) or for all k< i (low bit priority). Eo = 1 if E = 1 & Ii = 0 for all i, Gs = 1 if E = 1 & i s.t. Ii = 1.

E

(Gs is like A, and Eo tells us if enable is true or not).

1 2 3 4 5 6 7

E Eo Gs

I0 I7

y0 y1 y2 1 2

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Priority Encoder: Implement a 32-input priority encoder w/ 8 input priority encoders (high bit priority).

y32, y31, y30 I31-24 Eo Gs y22, y21, y20 I25-16 Eo Gs y12, y11, y10 I15-8 Eo Gs y02, y01, y00 I7-0 Eo Gs E

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Multiplexer

  • Definition
  • Logic Diagram
  • Application

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  • 3. Mux (Multiplexer) Definition: A digital

module that selects one of data inputs according to the binary address of the selector.

Description If E = 1 y = Di where i = (Sn-1, .. , S0) Else y = 0 E y D2n-1-D0 (Data input) Sn-1,0 (Selector)

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iClicker: Multiplexer Definition

  • A. A device that interleaves two or more activities
  • B. A communications device that combines several

signals for transmission over a single medium

  • C. A logic circuit that sends one of several inputs
  • ut over a single output channel.
  • D. The circuit that uses a common communications

channel for sending two or more messages or signals.

  • E. All of the above

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Multiplexer (Mux): Definition

  • Selects between one of N inputs to connect to the output.
  • log2N-bit select input – control input
  • Example: 2:1 Mux

Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 S D0 Y D1 D1 D0 S Y 1 D1 D0 S

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PI Q: What is the output of the following MUX?

  • A. 0
  • B. 1
  • C. Can’t say

E =1 y S=1 1 1

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Multiplexer Definition: Example

En y S1 S0 D0 D1 D2 D3 1 2 3

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S1 S0 y

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Multiplexer: Logic Diagram

  • Logic gates

– Sum-of-products form

Y D0 S D1

D1 Y D0 S S 00 01 1 Y 11 10 D0 D1 1 1 1 1 Y = D0S + D1S

  • Tristates

– For an N-input mux, use N tristates – Turn on exactly one to select the appropriate input

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Multiplexer Application

A B Y 1 1 1 1 1 Y = AB

00

Y

01 10 11

A B

  • Mux for a Boolean function with truth table as input

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Multiplexer: Application

A B Y 1 1 1 1 1 Y = AB A Y 1 1 A B Y B

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Multiplexer Application: universal set {Mux}

Example 1: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with an 8-input Mux.

Id a b c f 0 0 0 0 1 1 0 0 1 1 2 0 1 0 - 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1

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Multiplexer Application: universal set {Mux}

Example 1: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with an 8-input Mux.

Id a b c f 0 0 0 0 1 1 0 0 1 1 2 0 1 0 - 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1 En

y

1 1 1

a b c

S2 S1 S0

1 2 3 4 5 6 7 34

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E y a b

S1 S0 1 2 3

Example 2: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 4-input Muxes.

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a 1 1 b 1 1 c = 0 c = 1 D (c)

D0 (c) = D1 (c) = D2 (c) = D3 (c) =

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a 1 1 b 1 1 c = 0 1

  • c = 1

1 1 D (c)

D0 (c) =1 D1 (c) =0 D2 (c) =0 D3 (c) =c

E y 1 c a b

S1 S0 1 2 3

Example 2: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 4-input Muxes.

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a 1 00 01 10 11 1 1 - 0 0 0 0 1 D (b,c) D0 (b,c) D1 (b,c)

E

1 a

y Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2- input Muxes.

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a 1 00 01 10 11 1 1 - 0 0 0 0 1 D (b,c) D0 (b,c) D1 (b,c)

E b’

1 a

y

D0 (b,c) = b’ D1 (b,c) = bc 1

  • 1 0

c b 0 0 0 1 c b

Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2- input Muxes.

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D1 (b,c)

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D1 (b,c) b 1 c = 0 c = 1 1 l1(0) = 0 l1(c) = c

E b’

1 a

y Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2- input Muxes.

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D1 (b,c) b 1 c = 0 c = 1 1 l1(0) = 0 l1(c) = c

E E b’

1 a b

y

1

c Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2- input Muxes.

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  • 4. Demultiplexers

E x Control Input

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  • 4. Demultiplexers

E x y2n-1 -y0 S(n-1,0) Control Input yi = x if i = (Sn-1, .. , S0) & E=1 yi = 0 otherwise

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Shifters

  • Logical shifter: shifts value to left or right and fills empty

spaces with 0’s

– Ex: 11001 >> 2 = 00110 – Ex: 11001 << 2 = 00100

  • Arithmetic shifter: same as logical shifter, but on right

shift, fills empty spaces with the old most significant bit (msb).

– Ex: 11001 >>> 2 = 11110 – Ex: 11001 <<< 2 = 00100

  • Rotator: rotates bits in a circle, such that bits shifted off
  • ne end are shifted into the other end

– Ex: 11001 ROR 2 = 01110 – Ex: 11001 ROL 2 = 00111

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Shifter

Can be implemented with a mux s d yi

E 1 3 2 1 0

xi+1 xi-1 xi s d xn x0 x-1 xn-1 yn-1 y0

E

s d yi = xi-1 if E = 1, s = 1, and d = L = xi+1 if E = 1, s = 1, and d = R = xi if E = 1, s = 0 = 0 if E = 0

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Shifter Design

A3:0 Y3:0 shamt1:0

>> 2 4 4

A3 A2 A1 A0 Y3 Y2 Y1 Y0 shamt1:0

00 01 10 11

S1:0 S1:0 S1:0 S1:0

00 01 10 11 00 01 10 11 00 01 10 11

2

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Barrel Shifter

O or 1 shift O or 2 shift O or 4 shift

x s0 s1 s2

y 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

shift

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Shifters as Multipliers and Dividers

  • A left shift by N bits multiplies a number by 2N

– Ex: 00001 << 2 = 00100 (1 × 22 = 4) – Ex: 11101 << 2 = 10100 (-3 × 22 = -12)

  • The arithmetic right shift by N divides a number by 2N

– Ex: 01000 >>> 2 = 00010 (8 ÷ 22 = 2) – Ex: 10000 >>> 2 = 11100 (-16 ÷ 22 = -4)