Lecture 13: Standard Modules CSE 140: Components and Design - - PowerPoint PPT Presentation

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Lecture 13: Standard Modules CSE 140: Components and Design - - PowerPoint PPT Presentation

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Lecture 13: Standard Modules CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1 Decoder Application: universal set {Decoder, OR} Example:

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Lecture 13: Standard Modules

CSE 140: Components and Design Techniques for Digital Systems

Diba Mirza

  • Dept. of Computer Science and Engineering

University of California, San Diego

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Decoder Application: universal set {Decoder, OR}

Example: Implement the following functions with a 3-input decoder and OR gates. i) f1(a,b,c) = Σm(1,2,4) ii) f2(a,b,c) = Σm(2,3), iii) f3(a,b,c) = Σm(0,5,6)

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Decoder Application: universal set {Decoder, OR}

Example: Implement the following functions with a 2:4 decoder and OR gates. i) f1(a,b,c) = Σm(1,2,4)

How many 2:4 decoders are required to implement the above function? A. One B. Two C. Three D. Four

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Decoder Application: universal set {Decoder, OR}

Example: Implement the following functions with a 1:2 decoder and OR gates. i) f1(a,b,c) = Σm(1,2,4)

How many 1:2 decoders are required to implement the above function? A. Three B. Four C. Six D. Seven

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Tree of Decoders

Implement a 4-24 decoder with 3-23 decoders.

I0

y0 y1 y7

I1 I2

1 2 3 4 5 6 7

I0

y8 y9 y15

I1 I2

1 2 3 4 5 6 7

a d c b

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Implement a 6-26 decoder with 3-23 decoders.

En

D0

I2, I1, I0

D1 y0 y7 y8 y15 D7 y56 y63

En I2, I1, I0 I2, I1, I0 I5, I4, I3

Tree of Decoders

… …

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PI Q: A four variable switching function f(a,b,c,d) can be implemented using which of the following?

  • A. 1:2 decoders and OR gates
  • B. 2:4 decoders and OR gates
  • C. 3:8 decoders and OR gates
  • D. None of the above
  • E. All of the above

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Interconnect: Decoder, Encoder, Mux, DeMux

Processors Decoder: Decode the address to assert the addressed device Mux: Select the inputs according to the index addressed by the control signals

P1

Memory Bank

Mux

P2 Pk

Demux

Decoder

Mux

Data Address

Address k Address 2 Address 1 Data 1 Data k

Arbiter

n n-m m 2m

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  • 2. Encoder
  • Definition (What is it?)
  • Logic Diagram (How is it realized?)
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  • 2. Encoder: Definition

At most one Ii = 1. (yn-1,.., y0 ) = i if Ii = 1 & En = 1 (yn-1,.., y0 ) = 0 otherwise. A = 1 if En = 1 and one i s.t. Ii = 1 A = 0 otherwise. 8 inputs 3 outputs

y0 y1 y2

1 2 3 4 5 6 7

En A

I0 I7

1 2

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Encoder: Logic Diagram

En I1 I3 I5 I7 y0 En I2 I3 I6 I7 y1 En I4 I5 I6 I7 y2 En I0 I1 I6 I7 A . .

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Multiplexer

  • Definition
  • Logic Diagram
  • Application

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Interconnect: Decoder, Encoder, Mux, DeMux

Processors Decoder: Decode the address to assert the addressed device Mux: Select the inputs according to the index addressed by the control signals

P1

Memory Bank

Mux

P2 Pk

Demux

Decoder

Mux

Data Address

Address k Address 2 Address 1 Data 1 Data k

Arbiter

n n-m m 2m

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Multiplexer Definition: Example

En y S1 S0

D0 D1 D2 D3

1 2 3

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S1 S0 y

Selects between one of N inputs to connect to the output. log2N-bit select input – control input

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PI Q: What is the output of the following MUX for the given inputs and En=1, S=1?

  • A. 0
  • B. 1
  • C. Can’t say

En =1 y S=1

1

1

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Multiplexer (Mux): Example

2:1 Mux

Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 S D0 Y D1 D1 D0 S Y 1 D1 D0 S

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Multiplexer Application

A B Y 1 1 1 1 1 Y = AB

00

Y

01 10 11

A B

  • Mux for a Boolean function with truth table as input

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Multiplexer: Application

A B Y 1 1 1 1 1 Y = AB A Y 1 1 A B Y B

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Multiplexer Application: universal set {Mux}

Example 1: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with an 8-input Mux.

Id a b c f 0 0 0 0 1 1 0 0 1 1 2 0 1 0 - 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1

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Multiplexer Application: universal set {Mux}

Example 1: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with an 8-input Mux.

Id a b c f 0 0 0 0 1 1 0 0 1 1 2 0 1 0 - 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1 En

y

1 1 1

a b c

S2 S1 S0

1 2 3 4 5 6 7 20

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En y a b

S1 S0

1 2 3 Example 2: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 4-input Muxes.

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Id a b c f 0 0 0 0 1 1 0 0 1 1 2 0 1 0 - 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1

D0 (c) =1 D1 (c) =0 D2 (c) =0 D3 (c) =c

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a 1 1 b 1 1 c = 0 1

  • c = 1

1 1 D (c)

D0 (c) =1 D1 (c) =0 D2 (c) =0 D3 (c) =c

En y 1 c a b

S1 S0

1 2 3 Example 2: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 4-input Muxes.

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En 1

a

y Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2- input Muxes.

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Id a b c f 0 0 0 0 1 1 0 0 1 1 2 0 1 0 - 3 0 1 1 0 4 1 0 0 0 5 1 0 1 0 6 1 1 0 0 7 1 1 1 1

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D1 (b,c)

b 1 c = 0 c = 1 1 l1(0) = 0 l1(c) = c

En b’ 1

a

y Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2- input Muxes.

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D0 (b,c) = b’ D1 (b,c) = bc

1

  • 1 0

c b 0 0 0 1 c b

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D1 (b,c)

b 1 c = 0 c = 1 1 l1(0) = 0 l1(c) = c

En En b’ 1

a b

y 1 c Example 3: Given f (a,b,c) = Σm (0,1,7) + Σd(2), implement with 2- input Muxes.

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  • 4. Demultiplexers

En x Control Input

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  • 4. Demultiplexers

En x y2n-1 -y0 S(n-1,0) Control Input yi = x if i = (Sn-1, .. , S0) & En = 1 yi = 0 otherwise

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