Sidan 1 The Register File Zero ext . Branch 32 word (32 bit) - PDF document

Basic Building Blocks The Program Counter ■ There is a special register inside the processor. Multiplexer Adder Demultiplexer ■ Big enough to hold an instruction address (32 bits). ■ Called the program counter (PC). + Computer Engineering AddSub page 1 Computer Engineering AddSub page 2 Fetch - Execute Zero ext . Branch ■ Fetch: logic 0 A ALU – Send the value in the PC to the instruction memory. 4 B + – The instruction memory gives out one instruction. 31 + Sgn/Ze ■ Execute: extend – Carry out the fetched instruction. – Also: PC := PC+4; Fetch ≅ 10 8 times per second Execute Computer Engineering AddSub page 3 Computer Engineering AddSub page 4 Zero ext . Zero ext . Branch Branch logic 0 logic 0 A A ALU ALU 4 B 4 B + + 31 + 31 + Sgn/Ze Sgn/Ze extend extend Computer Engineering AddSub page 5 Computer Engineering AddSub page 6 Sidan 1

The Register File Zero ext . Branch ■ 32 word (32 bit) registers. logic 0 A ALU ■ r0 is special: 4 B + – Read: always zero. – Write: allowed, but won´t change it. 31 + Sgn/Ze ■ r31 is special: extend – Hard-wired return address (lab1). Computer Engineering AddSub page 7 Computer Engineering AddSub page 8 Add Instructions Zero ext . ■ 32 bit operands. Branch logic 0 A ALU 4 B + ■ Example: 6 5 5 5 – Add rd rs rt. Opcode rs rt rd 31 + Sgn/Ze – rd := rs + rt. extend ■ There is also: – Addu rd rs rt. Add rd rs rt ■ These are not add signed and add unsigned. The “u”-variant ignores overflow. Computer Engineering AddSub page 9 Computer Engineering AddSub page 10 Zero ext . Zero ext . Branch Branch logic 0 logic 0 A A ALU ALU 4 B 4 B + + 31 + 31 + Sgn/Ze Sgn/Ze extend extend Add rd rs rt Add rd rs rt Computer Engineering AddSub page 11 Computer Engineering AddSub page 12 Sidan 2

Zero ext . Zero ext . Branch Branch logic 0 logic 0 A A ALU ALU 4 4 B B + + 31 + 31 + Sgn/Ze Sgn/Ze extend extend Add rd rs rt Add rd rs rt Computer Engineering AddSub page 13 Computer Engineering AddSub page 14 Sub Instructions Zero ext . Branch ■ 32 bit operands. logic 0 A ALU 4 B + ■ Example: – Sub rd rs rt – rd := rs - rt 31 + Sgn/Ze extend ■ There is also: – Subu rd rs rt Add rd rs rt … next instr ■ These are not sub signed and sub unsigned The “u”-variant ignores overflow Computer Engineering AddSub page 15 Computer Engineering AddSub page 16 How to Negate Compare Instructions ■ Y := -X? ■ Signed integers: – Slt rd rs rt ■ Sub rd $0 rt ($0 means r0) – if rs < rt then rd := 1 else ■ rd := 0 - rt rd := 0 ■ Unsigned integers: ■ Careful: Neg ≠ Not – Sltu rd rs rt – if rs < rt then rd := 1 else rd := 0 Computer Engineering AddSub page 17 Computer Engineering AddSub page 18 Sidan 3

Immediate Variants Sign/Zero extension of the arithmetic instructions: ■ The immediate field is 16 bits Immediate ■ Addi rt rs Imm ■ Addiu rt rs Imm ■ But most operations work on 32 bits! ■ Slti rt rs Imm Zero extension Sign extension ■ Sltiu rt rs Imm Immediate Immediate 0000000000000000 xxxxxxxxxxxxxxxx x ■ Imm sign-extend 31 16 15 0 31 16 15 0 ■ No sub instruction Bit 15, the Sign bit, is copied into bits 16 - 31 Computer Engineering AddSub page 19 Computer Engineering AddSub page 20 Zero ext . Zero ext . Branch Branch logic 0 logic 0 A A ALU ALU 4 4 B B + + 31 + 31 + Sgn/Ze Sgn/Ze extend extend Addi rt rs Imm Computer Engineering AddSub page 21 Computer Engineering AddSub page 22 Zero ext . Zero ext . Branch Branch logic 0 logic 0 A A ALU ALU 4 B 4 B + + 31 + 31 + Sgn/Ze Sgn/Ze extend extend Addi rt rs Imm Addi rt rs Imm Computer Engineering AddSub page 23 Computer Engineering AddSub page 24 Sidan 4

Zero ext . Zero ext . Branch Branch logic 0 logic 0 A A ALU ALU 4 4 B B + + 31 + 31 + Sgn/Ze Sgn/Ze extend extend Addi rt rs Imm Addi rt rs Imm … next instr Computer Engineering AddSub page 25 Computer Engineering AddSub page 26 Sidan 5