[PPT] - Computer Architecture: Lecture 6 Multicycle MIPS Implementation PowerPoint Presentation

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Computer Architecture: Lecture “6” Multicycle MIPS Implementation

“Severe 100% midterm advisory”
Thursday!!

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Single-Cycle CPU Summary

Fairly straightforward
Which instruction takes the longest?

By how much? Why is that a problem?

Execution time = insts * cpi * cycle

time Most machines are not single-cycle.

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Evaluating Critical Path

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.9 1 1 beq 3.9

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1 1 Store 4.7 .8 1

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1 1 Load 3.7 .8

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1 1 R-type Total R-Write D mem PC update ALU Decode, R-Read I mem

MemtoReg MemRead MemWrite ALUOp ALUSrc RegDst PC Instruction memory Read address Instruction [31–0] Instruction [20–16] Instruction [25–21] Add Instruction [5–0] RegWrite 4 16 32 Instruction [15–0] Registers Write register Write data Write data Read data 1 Read data 2 Read register 1 Read register 2 Sign extend ALU result Zero Data memory Address Read data M u x 1 M u x 1 M u x 1 M u x 1 Instruction [15–11] ALU control Shift left 2 PCSrc ALU Add ALU result

Insight: Different instructions have different critical paths!

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Multicycle design

Problem: In single-cycle design, cycle time must be long

enough for longest instruction

Solution: break execution into smaller tasks
each task takes a cycle;
different instructions require different numbers of cycles
Another advantage: we can multiplex area-intensive datapath

components (memories, ALUs, etc) and use them multiple times for a given instruction (as long as each use is on a different cycle.) This used to be one of the key desirable features of multicycle – not so much anymore..

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Idea: quantize instruction execution into smaller steps

Five execution steps (some instructions use

fewer)

IF: Instruction Fetch
ID: Instruction Decode (& register fetch & add PC+immed)
EX: Execute
Mem: Memory access
WB: Write-Back into registers

3.0

.1

.9 1 1 beq 3.9

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1 1 Store 4.7 .8 1

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1 1 Load 3.7 .8

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1 1 R-type Total R- Write D cache PC update ALU Decode, R-Read I cache

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Will multicycle be faster? Depends on program + stage timings

10% 3 beq 10% 4 Store 20% 5 Load 60% 4 R-type Instruction frequency Cycles needed

Single cycle design:

Clock cycle time = 4.7ns time/inst = 1 cycle/inst * 4.7 ns/cycle = 4.7 ns/inst

Multicycle design:

Clock cycle time = 1 ns time/inst = CPI * 1 ns/cycle =

What is CPI assuming this instruction mix???

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Adding State Elements

Since execution takes place over multiple cycles, and we reuse some

f the hardware, we need to

capture intermediate results. Need extra registers when:

signal is computed in one clock cycle and

used in another, AND

the inputs to the combinational circuit

can change before the signal is written into a state element.

We only require them to be “held” for 1

cycle

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Where to add registers (more or less)

P C Instruction memory Read address Instruction 16 32 Add ALU result M u x Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Shift left 2 4 M u x ALU operation 3 RegWrite MemRead MemWrite PCSrc ALUSrc MemtoReg ALU result Zero ALU Data memory Address

Write

data Read data M u x Sign extend Add

IF ID Ex Mem WB

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Merging Logic from Single Cycle to MultiCycle

Shift left 2 PC M u x 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15–11] M u x 1 M u x 1 4 Instruction [15–0] Sign extend 32 16 Instruction [25–21] Instruction [20–16] Instruction [15–0] Instruction register ALU control ALU result ALU Zero Memory data register A B

IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op [5–0]

Instruction [31-26] Instruction [5–0]

M u x 2 Jump address [31-0]

Instruction [25–0] 26 28

Shift left 2 PC [31-28]

1 1 M u x 3 2 M u x 1 ALUOut Memory MemData Write data Address

P C Instruction memory Read address Instruction 16 32 Add ALU result M u x Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Shift left 2 4 M u x ALU operation 3 RegWrite MemRead MemWrite PCSrc ALUSrc MemtoReg ALU result Zero ALU Data memory Address

Write

data Read data M u x Sign extend Add

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Multicycle Datapath – let’s figure out basic execution model

Shift left 2 PC M u x 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15–11] M u x 1 M u x 1 4 Instruction [15–0] Sign extend 32 16 Instruction [25–21] Instruction [20–16] Instruction [15–0] Instruction register ALU control ALU result ALU Zero Memory data register A B

IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op [5–0]

Instruction [31-26] Instruction [5–0]

M u x 2 Jump address [31-0]

Instruction [25–0] 26 28

Shift left 2 PC [31-28]

1 1 M u x 3 2 M u x 1 ALUOut Memory MemData Write data Address

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Summary of execution steps

Step R -type M em ory B ranch Instruction Fetch IR = M em [PC ] PC = PC + 4 Instruction D ecode/ register fetch A = R eg[IR [25-21]] B = R eg[IR [20-16]] A L U out = PC + (sign-extend(IR [15-0]) < < 2) E xecution, address com putation, branch com pletion A L U out = A op B A L U out = A + sign- extend(IR [15-0]) if (A = =B ) then PC = A L U out M em ory access or R - type com pletion R eg[IR [15-11]] = A L U out m em ory-data = M em [A L U out]

r

M em [A L U out]= B W rite-back R eg[IR [20-16]] = m em ory-data

This is Register Transfer Language (RTL)

“High level” description of changes to state elements

We’ll go through these in exacting detail

And translate them to “low level” control signal settings Modern design tools do this automatically

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Multicycle Datapath – let’s figure out control logic

Shift left 2 PC M u x 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15–11] M u x 1 M u x 1 4 Instruction [15–0] Sign extend 32 16 Instruction [25–21] Instruction [20–16] Instruction [15–0] Instruction register ALU control ALU result ALU Zero Memory data register A B

IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite Control Outputs Op [5–0]

Instruction [31-26] Instruction [5–0]

M u x 2 Jump address [31-0]

Instruction [25–0] 26 28

Shift left 2 PC [31-28]

1 1 M u x 3 2 M u x 1 ALUOut Memory MemData Write data Address

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Shift left 2 Memory MemData Write data M u x 1 Instruction [15–11] M u x 1 4 Instruction [15–0] Sign extend 32 16 Instruction [25–21] Instruction [20–16] Instruction [15–0] Instruction register ALU control ALU result ALU Zero Memory data register A B

IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite Control Outputs Op [5–0]

Instruction [31-26] Instruction [5–0]

M u x 2 Jump address [31-0]

Instruction [25–0] 26 28

Shift left 2 PC [31-28]

1 Address EPC

CO 00 00 00

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Cause

ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite EPCWrite IntCause CauseWrite

1 1 M u x 3 2 M u x 1 M u x 1 PC M u x 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 ALUOut Shift left 2 Memory MemData Write data M u x 1 Instruction [15–11] M u x 1 4 Instruction [15–0] Sign extend 32 16 Instruction [25–21] Instruction [20–16] Instruction [15–0] Instruction register ALU control ALU result ALU Zero Memory data register A B

IorD MemRead MemWrite MemtoReg PCWriteCond PCWrite IRWrite Control Outputs Op [5–0]

Instruction [31-26] Instruction [5–0]

M u x 2 Jump address [31-0]

Instruction [25–0] 26 28

Shift left 2 PC [31-28]

1 Address EPC

CO 00 00 00

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Cause

ALUOp ALUSrcB ALUSrcA RegDst PCSource RegWrite EPCWrite IntCause CauseWrite

1 1 M u x 3 2 M u x 1 M u x 1 PC M u x 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 ALUOut

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