Multicycle Approach CSE 675.02: Introduction to Computer - PowerPoint PPT Presentation

Multicycle Approach CSE 675.02: Introduction to Computer Architecture • We will be reusing functional units Designing – ALU used to compute address and to increment PC MIPS Processor – Memory used for instruction and data • Our control signals will not be determined (Multi-Cycle) directly by instruction Presentation H – e.g., what should the ALU do for a “subtract” instruction? Slides by Gojko Babi ć and Elsevier Publishing • We’ll use a finite state machine for control 08/08/2005 Instructions from ISA Multicycle Approach perspective • Break up the instructions into steps, each step takes a cycle • Consider each instruction from perspective of ISA. – balance the amount of work to be done • Example: – restrict each cycle to use only one major functional unit – The add instruction changes a register. • At the end of a cycle – Register specified by bits 15:11 of instruction. – store values for use in later cycles (easiest thing to do) – Instruction specified by the PC. – introduce additional “internal” registers – New value is the sum (“op”) of two registers. – Registers specified by bits 25:21 and 20:16 of the instruction 0 PC Read 0 Instruction M Reg[Memory[PC][15:11]] <= Reg[Memory[PC][25:21]] M u Address [25–21] register 1 Read u x A data 1 x Instruction 1 Read op Memory 1 Zero [20–16] register 2 0 MemData ALU ALU Instruction Registers M ALUOut Reg[Memory[PC][20:16]] Write result [15–0] Instruction u Read x register 0 Write [15–11] B data 2 1 Instruction 1 M data 4 u register Write 0 2 x data – In order to accomplish this we must break up the instruction. M Instruction 3 u [15–0] x (kind of like introducing variables when programming) 1 16 32 Memory Sign Shift data extend left 2 register g. babic Presentation H 4

Breaking down an instruction Idea behind multicycle approach • ISA definition of arithmetic: • We define each instruction from the ISA perspective (do this!) Reg[Memory[PC][15:11]] <= Reg[Memory[PC][25:21]] op • Break it down into steps following our rule that data flows through at Reg[Memory[PC][20:16]] most one major functional unit (e.g., balance work across steps) • Introduce new registers as needed (e.g, A, B, ALUOut, MDR, etc.) • Could break down to: – IR <= Memory[PC] • Finally try and pack as much work into each step – A <= Reg[IR[25:21]] (avoid unnecessary cycles) – B <= Reg[IR[20:16]] while also trying to share steps where possible (minimizes control, helps to simplify solution) – ALUOut <= A op B – Reg[IR[20:16]] <= ALUOut • Result: Our book’s multicycle Implementation! • We forgot an important part of the definition of arithmetic! – PC <= PC + 4 g. babic Presentation H 5 g. babic Presentation H 6 Five Execution Steps Step 1: Instruction Fetch • Instruction Fetch • Use PC to get instruction and put it in the Instruction Register. • Instruction Decode and Register Fetch • Increment the PC by 4 and put the result back in the PC. • Can be described succinctly using RTL "Register-Transfer • Execution, Memory Address Computation, or Branch Language" Completion IR <= Memory[PC]; • Memory Access or R-type instruction completion PC <= PC + 4; • Write-back step Can we figure out the values of the control signals? What is the advantage of updating the PC now? INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!

Step 2: Instruction Decode and Step 3 (instruction dependent) Register Fetch • ALU is performing one of three functions, based on • Read registers rs and rt in case we need them instruction type • Compute the branch address in case the instruction is a branch • Memory Reference: • RTL: ALUOut <= A + sign-extend(IR[15:0]); A <= Reg[IR[25:21]]; B <= Reg[IR[20:16]]; • R-type: ALUOut <= PC + (sign-extend(IR[15:0]) << 2); ALUOut <= A op B; • We aren't setting any control lines based on the instruction type • Branch: (we are busy "decoding" it in our control logic) if (A==B) PC <= ALUOut; Step 4 (R-type or memory- Write-back step access) • Loads and stores access memory • Reg[IR[20:16]] <= MDR; MDR <= Memory[ALUOut]; or Memory[ALUOut] <= B; Which instruction needs this? • R-type instructions finish Reg[IR[15:11]] <= ALUOut; The write actually takes place at the end of the cycle on the edge

Simple Questions Summary: • How many cycles will it take to execute this code? lw $t2, 0($t3) lw $t3, 4($t3) beq $t2, $t3, Label #assume not add $t5, $t2, $t3 sw $t5, 8($t3) Label: ... • What is going on during the 8th cycle of execution? • In what cycle does the actual addition of $t2 and $t3 takes place? Review: finite state machines PCWriteCond PCSource PCWrite Outputs ALUOp • Finite state machines: IorD ALUSrcB MemRead Control ALUSrcA MemWrite – a set of states and Op RegWrite MemtoReg [5–0] IRWrite 0 – next state function (determined by current state and the input) RegDst Jump M 1 u address Shift x – output function (determined by current state and possibly input) 26 28 Instruction [25-0] [31–0] left 2 2 Instruction [31–26] PC [31–28] 0 PC 0 Instruction Read M M Address [25–21] register 1 Next u Read u x A state data 1 x Instruction 1 Read Memory 1 Zero Next-state [20–16] Current state register 2 function 0 MemData ALU ALU Instruction Registers M ALUOut result Write [15–0] Instruction u Read x register 0 [15–11] B Write data 2 Clock 1 Instruction M data 4 1 u Inputs register Write 0 2 x data M Instruction 3 u [15–0] x 1 Output Outputs Memory function 16 32 ALU data Sign Shift control register extend left 2 – We’ll use a Moore machine (output based only on current state) Instruction [5–0] g. babic Presentation H 15

Review: finite state machines Implementing the Control • Value of control signals is dependent upon: – what instruction is being executed • Example: – which step is being performed B. 37 A friend would like you to build an “electronic eye” for • Use the information we’ve accumulated to specify a use as a fake security device. The device consists of three finite state machine lights lined up in a row, controlled by the outputs Left, Middle, and Right, which, if asserted, indicate that a light should be – specify the finite state machine graphically, or on. Only one light is on at a time, and the light “moves” from – use microprogramming left to right and then from right to left, thus scaring away thieves who believe that the device is monitoring their activity. • Implementation can be derived from specification Draw the graphical representation for the finite state machine used to specify the electronic eye. Note that the rate of the eye’s movement will be controlled by the clock speed (which should not be too great) and that there are essentially no inputs. Finite State Machine Example: Finite State Machines 3 ones… Introduction Draw the FSM… Truth table… PS Input NS Output 00 0 00 0 00 1 01 0 01 0 00 0 01 1 10 0 10 0 00 0 10 1 00 1 g. babic Presentation H 19 g. babic Presentation H 20

Finite State Machines Hardware • A current state is kept in the Current state register. Implementation of FSM • Next state function is determined by current state and the input. • Output function is determined by current state and input. • We will use a Moore machine, where output is based only on current state. + N e xt state N e xt-state C u rre nt state func tio n C lock = ? Inp uts O u tp ut O utpu ts Figure B.10.1 func tio n g. babic Presentation H 21 g. babic Presentation H 22 Finite State Machine Graph for Control Unit Graphical Specification Instruction fetch Instruction decode/ register fetch MemRead of FSM 0 ALUSrcA = 0 1 IorD = 0 ALUSrcA = 0 IRWrite Start ALUSrcB = 11 ALUSrcB = 01 Instruction decode/ ALUOp = 00 ALUOp = 00 Instruction fetch register fetch 0 PCWrite M em R ead 1 PCSource = 00 • Note: ALUSrcA = 0 IorD = 0 ALUSrcA = 0 IRW rite ALUSrcB = 11 Start ALUSrcB = 01 ALUO p = 00 ALUO p = 00 – don’t care if not mentioned PCW rite PC Source = 00 (Op = R-type) ) Q ' E (Op = 'J') B – asserted if name only ' = (Op = 'LW ') or (Op = 'SW ') p M emory address O Branch ( Jump com putation Execution com pletion completion ALUSrcA=0 – otherwise exact value Memory address Branch Jump 2 6 8 9 ALUSrcB=01 computation Execution completion completion ALUSrcA = 1 ALUSrcA = 1 ALUSrcB = 00 ALUOp=01 ALUSrcA = 1 2 6 8 9 PCW rite ALUSrcB = 10 ALUO p = 01 ALUSrcB = 00 PC Source = 10 ALUOp = 00 ALUSrcA = 1 PC W riteCond ALUO p = 10 ALUSrcA = 1 ALUSrcA = 1 ALUSrcB = 00 PCWrite PC Source = 01 ALUSrcB = 10 ALUSrcB = 00 PCSource = 10 ALUOp = 01 ALUOp = 00 ALUOp = 10 (Op = 'SW') PCWriteCond (Op = 'LW') PCSource = 01 • How many state M emory M em ory access access R-type com pletion Memory Memory 3 5 7 access access R-type completion bits will we need? RegD st = 1 3 5 7 Mem Read M em W rite RegW rite IorD = 1 IorD = 1 M em toReg = 0 RegDst = 1 MemRead MemWrite RegWrite IorD = 1 IorD = 1 Figure 5.38 MemtoReg = 0 with corrections W rite-back step 4 in red Memory read R egDst = 0 completon step RegW rite M em toR eg = 1 4 RegDst = 1 RegWrite g. babic Presentation H 23 MemtoReg = 0