Analog Mixed signal Analog Mixed signal Examiners: Prof. Henrik - - PowerPoint PPT Presentation

ETI210 – IC Project and Verification

IC Project 2008 Introduction

Examiners: Prof. Henrik Sjöland (Analog+ Mixed)

• Dr. Joachim Rodrigues (Digital + Computer)

IC Project 2010 Introduction

IC Design Challenges

Limited bandwidth Thermal noise Process variations Device nonlinearity Device mismatch Limited model accuracy Increased complexity Slow simulations Crosstalk Substrate noise A+D co-simulation

Analog Analog Mixed signal Mixed signal

Supply noise

Large project

Time frame:

• Projects start now
• Circuits sent for fabrication: ~June 2011
• Circuits back for measurements: ~September 2011

Groups:

• 3 students per group

Important:

• Make & follow time‐plan
• Systematic approach

Time plan bullets

• Literature search and studies
• System simulations
• Choice of circuit topologies, hand calculations
• Circuit simulations
• Layout work
• Measurements
• Writing of report (distributed)

Recommend 1 meeting/wk with supervisor

Teaching Top Down Design Methodology through IC Design Projects Project input Project execution Project examination Analog & Mixed IC Projects 2010 Rough Timeplan

• HT LP2 (15 December’10) – System model review.

Study phase as well as designing and simulating a structural system model.

• VT LP1 (1 March’11) – Schematic design review.

Schematic level design and simulations

• VT LP2 (15 May’11) – Tape-Out design review.

Layout and post layout simulations

• HT LP1 (15 October’11)

Measurement verification

• Hand in design report

Requirements

• Passed Analog IC exam
• (Passed Digital IC exam)
• 9 credits:

– Design and implementation of a circuit prototype in UMC 130-nm CMOS – 3 Design reviews (project milestones) – Written design report

• 3 credits:

– Measurement verification & report

• Completing the course, total 12 credits.

IC Project 1: Audio Class D Amplifier

• Switched mode amplifier
• Self oscillating with hysteresis
• High loop gain
• Introduce dead time with comparator offset

‐ minimal delay ‐> maximize loop gain

• Goals:

High efficiency low THD+N Supervised by Carl Bryant

Diff-control ring oscillator Differential CP Pulse sampled LPF Continuous VCO tuning bank adjusting

Specification

25MHz reference 1GHz output <-110dBc/Hz@1MHz

Supervised by Ping Lu and Andreas Axholt

IC Project 2: PLL for Gbit Ethernet IC‐projects 3,4: Delta‐Sigma A/D‐Converters

Supervised by Dejan Radjen & Mattias Andersson

• Two projects:
• Audio

– Hearing‐aid applications – Supervisor: Dejan

• Telecommunication (GSM)

– 100kHz bandwidth – Supervisor: Mattias

DAC H(s) vd[n] clk va(t) vc(t) clk

∫

Delta-Sigma Analog/Digital Converter

IC Project 5: FM radio receiver front‐end

• LNA + Mixer + QLO generation
• Specifications

– Conv. Gain 20dB – NF < 4dB – S11 < ‐10dB – IIP3 < ‐5dBm – IRR > 40 dB

LNA RF QLO BB

88-108 MHz 87.5-107.5 MHz

Supervised by Martin Liliebladh

Div 2

175-215 MHz

2xLO

IC Project 6: Buck‐Boost DC‐DC Converter

Supervised by Jonas Lindstrand

• Buck‐Boost DC‐DC Converter
• Off‐chip Inductor (L)
• Self Oscillating System

Main Goals :

• High Efficiency
• High Output Power (VOut ≥ 2∙VDD)
• Low Switching Noise @ Output

Apply for a project now!

Talk to the supervisors:

• Jonas Lindstrand
• Carl Bryant
• Dejan Radjen
• Mattias Andersson
• Ping Lu
• Andreas Axholt
• Martin Liliebladh
• r to the course manager Henrik Sjöland