Variation is the Future March 17 th 2014 Andrew C. R. Angus 1 , Fikru - - PowerPoint PPT Presentation

Statistical Design and Verification of Analogue Systems

Variation is the Future

Andrew C. R. Angus1, Fikru Adamu-Lema3, Asen Asenov34, Binjie Cheng4, Campbell Millar4, Neil Munro2, Alan Murray1, John Pennock2, Neil Rankin2

School of Engineering, University of Edinburgh1 Device Modelling Group, University of Glasgow3 Wolfson Microelectronics2 Gold Standard Simulations (GSS)4

March 17th 2014

Contents

• Variation in Deep-Submicron CMOS
• StatDes
• Fabricated Test Chip
• Compact Model Extraction
• Local Mismatch Plots [Tuinhout CICC13]
• Pelgrom Area Scaling
• The Future?

Statistical Design and Verification of Analogue Systems

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Variation in Deep-Submicron CMOS

• Industry pressures continue to shrink process nodes
• Consumer desires smarter, lower-power devices
• Technologies are optimised for the majority (digital) devices
• Analogue/Mixed-Signal still crucial for functioning Systems-on-Chip
• Active device area is now reaching a point where the discrete nature of

charge and matter are noticeably impacting device performance.

• Key processing steps are stochastic
• intrinsic variation in device performance
• overwhelms the contributions of process gradients (small-to-medium devices)
• Correct understanding of variability is essential
• identify problematic circuit elements
• reduce overdesign of circuit blocks where there is no benefit.

Statistical Design and Verification of Analogue Systems

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Traditional Analogue Solution

• Methodology: spend area to mitigate

variation

• Increasingly costly with each node shrink
• Careful layout -> good matching
• Consistency of environment
• Symmetry
• Inter-digitation
• Dummy structures
• Layout reduces systematic mismatch
• Active area reduces intrinsic mismatch

Statistical Design and Verification of Analogue Systems

Symmetrical differential-pair layout with a ring of dummy devices.

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• Opportunities for alternatives available (system-level solutions)
• Digital sections are cheap
• Calibration, reconfiguration and post-processing (digitally assisted analogue).

Intrinsic Variation Sources

Statistical Design and Verification of Analogue Systems

Atomistic device simulation can help quantify the impact on device performance.

LER MGG

RDF + LER + MGG

SANDIA Labs Ohmori, IEDM’08 Inoue ‘09 5 17/03/2014

Line Edge Roughness (LER) Metal Gate Granularity (MGG) Random Dopant Fluctuation (RDF)

• A collaborative project between academia and industry to

investigate intrinsic variability of deep-submicron devices for analogue circuits.

• Primary goal is to verify the compact model extraction and

statistical simulation tools developed by academia and show how they can be used to augment the existing tool-chains in use by industry.

• Phase One: Test Chip Design and Fabrication (65nm bulk CMOS)
• Phase Two: Measurement and Compact Model Extraction
• Phase Three: Verification and Statistical Simulation (Current Work)

Statistical Design and Verification of Analogue Systems

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StatDes

• Devs. OA Differential pairs OAs Devices

n large p n alpha p n

Statistical Design and Verification of Analogue Systems

Fabricated Test Chip

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• Common 32-pad ring structure used for all modules
• 13 modules of devices, differential-pairs and basic Operational Amplifiers:
• Devices: 14 per module (common bulk and gate connections)
• Diff-pairs: 7 pairs per module (common bulk and gate connections)
• Op-Amps: 8 per module (two-stage, Miller compensated)
• 78 instances of the test chip were available for measurement using probe-

stations at Glasgow and Edinburgh Universities.

Capacitor

80µm pch devices OAs

Statistical Design and Verification of Analogue Systems

Fabricated Test Chip

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• Individual device characterisation

is very area intensive

• More informative structures:
• Individual gate connections
• Repeated differential-pairs (closer

proximity) rather than more dimensions

150x60nm

Mystic LibraryMaker I-V characteristic data Device models Generative or LUT device library Template Netlist RandomSpice (supports parallel grid computation option) Statistical Simulation Results Post-processor and/or results database

Model Extraction Statistical Circuit Simulation

• GSS Mystic: I-V characteristics -> compact models
• Initial nominal extraction requires manual intervention (selection/tuning)
• Subsequent fitting of statistical parameters is automated and quick
• Constructed device libraries:
• Device Look-up Tables (LUTs)
• Generative models (derived from parameter distributions)
• In this work compact models extracted from device measurements
• Alternatively this data could be obtained through atomistic simulation
• Individual variation sources
• Technologies not yet in production

Statistical Design and Verification of Analogue Systems

Compact Model Extraction

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The result is fitted models accurate across the full operating range of the device.

Statistical Design and Verification of Analogue Systems

Compact Model Extraction

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Statistical Design and Verification of Analogue Systems

Statistical Simulation

Mystic LibraryMaker I-V characteristic data Device models Generative or LUT device library Template Netlist RandomSpice (supports parallel grid computation option) Statistical Simulation Results Post-processor and/or results database

Model Extraction Statistical Circuit Simulation 11 17/03/2014

• GSS RandomSpice:
• Template netlist driven work-flow (library specific model keywords)
• Creates specific netlist instances from LUT or generative models
• Simulation performed sequentially or submitted to a compute grid
• Data management support:
• Potential for vast numbers of data
• User-scripted post-processing modules
• Backend database storage

20 40 60 80 100 120 0.2 0.4 0.6 0.8 1 1.2

Drain Current Mismatch σ(%ΔId/‹Id›) Gate Voltage (V)

pch 150x60nm nch 150x60nm pch 600x60nm nch 600x60nm

Vds=1.2V Vbs = 0V

Local mismatch variation plot of drain current against gate voltage for small geometry devices in saturation extracted from differential pair measurements. Useful tool for investigating the impact of parametric gradients on device

• matching. Tuinhout et al have found that careful attention to the layout is more

important for matching than keeping a short distance between the components. Idsat

Statistical Design and Verification of Analogue Systems

Local Mismatch Plots [Tuinhout CICC13]

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yp = 0.7485x yn = 0.9291x

2 4 6 8 10 12 2 4 6 8 10 12

Drain Current Mismatch σ(%ΔId/‹Id›) (WL)^-0.5 (µm-1)

%Id pch %Id nch %Id nch meas Linear (%Id pch) Linear (%Id nch)

Vgs =Vds=1.2V Vbs = 0V

Pelgrom plot of drain current mismatch for eight device geometries. Area scaling continues to be applicable with a slightly better per area matching of pch devices.

Statistical Design and Verification of Analogue Systems

Pelgrom Area Scaling

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150x60nm 600x600nm

The Future?

• Current CAD/EDA tools generally support the use of statistical

models and simulation of circuit designs to verify their behaviour.

• This provides necessary confidence that a circuit block will yield

correctly when manufactured

• However, on its own this does not provide insight into what

elements are sensitive to variation or should be modified to reduce

• verdesign.
• Tools should further support statistical analysis and data mining of

simulation results

• augment designer expertise
• allow for a rapid exploration of the design space
• ensure variation-awareness from the initial nominal design.

Statistical Design and Verification of Analogue Systems

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Questions?

Statistical Design and Verification of Analogue Systems

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