MVD Strip ASIC (PASTA) Status Update of the PA NDA St rip A SIC Andr - - PowerPoint PPT Presentation

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MVD Strip ASIC (PASTA) Status Update of the PA NDA St rip A SIC Andr - - PowerPoint PPT Presentation

May 17, 2023 318 likes •607 views

MVD Strip ASIC (PASTA) Status Update of the PA NDA St rip A SIC Andr Goerres Mitglied der Helmholtz-Gemeinschaft 10 September 2013 46. PANDA Meeting, Ruhr-University-Bochum 1 Content Introduction to TOFPET/PASTA Status of analogue

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SLIDE 1

Mitglied der Helmholtz-Gemeinschaft

MVD Strip ASIC (PASTA)

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Status Update of the PANDA Strip ASIC

André Goerres 10 September 2013

  • 46. PANDA Meeting, Ruhr-University-Bochum
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SLIDE 2

Mitglied der Helmholtz-Gemeinschaft

Content

  • Introduction to TOFPET/PASTA
  • Status of analogue part

– Front-end and TDC

  • Status of digital part

– Meeting in Lisbon – Redesign of TDC Control

2

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SLIDE 3

Mitglied der Helmholtz-Gemeinschaft

Motivation for using Time-of-Flight in PET

3

Normal PET operation

  • Introduce positron-emitting

radionuclide (β+ decay) into patients body, detect annihilation gamma rays.

  • Position of annihilation somewhere

along the line of response (LOR).

  • 2D information by superimposing

different LORs.

PET: Positron Emission Tomography

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SLIDE 4

Mitglied der Helmholtz-Gemeinschaft

Motivation for using Time-of-Flight in PET

3

Normal PET operation

  • Introduce positron-emitting

radionuclide (β+ decay) into patients body, detect annihilation gamma rays.

  • Position of annihilation somewhere

along the line of response (LOR).

  • 2D information by superimposing

different LORs. PET using Time-of-Flight (TOF)

  • Again, β+ radionuclide in body.
  • Measure time difference of arriving

photons (accuracy ~200 ps ⇒ 3 cm).

  • Additional position information

alongside LOR.

  • Higher SNR of reconstructed image
  • Shorter exam time and

reduced injected dose

PET: Positron Emission Tomography TOFPET ASIC developed by LIP Lisbon in the FP7/EndoTOFPET-US project

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SLIDE 5

Mitglied der Helmholtz-Gemeinschaft

Concept of the ASIC

  • Readout SiPM, achieve:

– High time resolution and reduce dark count rate

  • Two TDCs per channel

– Time and energy branch

(low and high threshold)

– Energy trigger (t2) validates time trigger (t1)

  • Charge by time-over-

threshold (ToT)

– ToT measurement: t3 - t1 – Time binning: 50 ps (25 ps optional)

4

U t t1 t3 UT UE t2

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SLIDE 6

TDC Control analogue TDC front-end Global Controller

4x TDCT 4x TDCT 4x TDCT 4x TDCT

Mitglied der Helmholtz-Gemeinschaft

Concept of the ASIC

  • Four stages:

– Front-end (analogue) – TDC (analogue) – TDC Control (digital) – Global Controller (digital)

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PreAmp thrT thrE 4x TDCT 4x TDCE TDC_CTRLT TDC_CTRLE hit- validation data register

  • utput

buffer

ch0

CLK config.

LVDS clock LVDS config LVDS data

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SLIDE 7

TDC Control analogue TDC front-end Global Controller

4x TDCT 4x TDCT 4x TDCT 4x TDCT

Mitglied der Helmholtz-Gemeinschaft

Concept of the ASIC

  • Four stages:

– Front-end (analogue) – TDC (analogue) – TDC Control (digital) – Global Controller (digital)

5

PreAmp thrT thrE 4x TDCT 4x TDCE TDC_CTRLT TDC_CTRLE hit- validation data register

  • utput

buffer

ch0

TDC Control analogue TDC front-end

4x TDCT 4x TDCT 4x TDCT 4x TDCT PreAmp thrT thrE 4x TDCT 4x TDCE TDC_CTRLT TDC_CTRLE hit- validation

ch1 ch2

. . .

data register CLK config.

LVDS clock LVDS config LVDS data

data register

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SLIDE 8

Mitglied der Helmholtz-Gemeinschaft

Analogue Time-to-Digital Converter

  • Two stages: buffer and convert signal

– Buffering: discharge a capacitor (TAC)

  • Start: threshold; End: rising edge of clock*

– Transfer to 4x larger capacitor, linearly recharge with 32/64x smaller current (Wilkinson ADC)

  • Increase time resolution by 128/256x (50/25 ps @ 160 MHz)

– Conversion takes ~ 3 µs (@128x) → buffer multiplicity of 4

6

front-end

stage 1

analogue TDC

stage 2

TDC CTRL

stage 3

global CTRL

stage 4

time branch energy branch

ADC ADC

VTAC t

write TAC

Vref

VADC t

transf.

Vref

conversion

ADC: Analogue to Digital Converter TAC: Time to Analogue Converter *: Dynamic range 1-3 clock cycles

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SLIDE 9

Mitglied der Helmholtz-Gemeinschaft

Floorplan of TOFPET ASIC v1

  • CMOS 130 nm (IBM), 64 channels on 25 mm2
  • One pad-free edge to attribute two twin chips back-to-back

7

Highlighted areas: bias and calibration circuitry

Discussion afterwards

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SLIDE 10

Mitglied der Helmholtz-Gemeinschaft

Readout of MVD Silicon Strips

  • General parameters match the MVD requirements
  • Differences to solve:

– Signal shape / capacitance ⇒ redesign analogue part – Channel pitch ⇒ tighter layout for channels? Positioning? – Power consumption ⇒

  • Bug in front-end stage
  • Slower clock (40 MHz?), clock gating
  • Redesign digital TDC control
  • Tune analogue part

8

Area

  • Ch. pitch

Hit rate

Time bin.

CLK Power TOFPET MVD ¡req. 7.1 x 3.5 mm2 102 µm < 100 kHz 50 ps 80-160 MHz 7-8 mW/ch < 8 x 8 mm2 ≈ 50 µm < 40 kHz < 20 ns 155.56 MHz < 4 mW/ch

Discussion afterwards

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SLIDE 11

Mitglied der Helmholtz-Gemeinschaft

PASTA Status Update

9

Analogue Part

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SLIDE 12

Mitglied der Helmholtz-Gemeinschaft

Front-end: Complete Redesign

  • Different signal shape lead to complete redesign of analogue

front-end

– Introducing a second amplifying stage (less cross talk)

  • Linearity of input charges:

10

simulations by Valentino Di Pietro

MIP signal

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SLIDE 13

Mitglied der Helmholtz-Gemeinschaft

Analogue TDC to UMC

  • Analogue converted to UMC

– Included an additional current mirror – Stability of TDC charging current improved:

11

IBM UMC

simulations by Alberto Riccardi

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SLIDE 14

Mitglied der Helmholtz-Gemeinschaft

Temperature Stability of TDC

  • Conversion time in TDC, depending on temperature
  • Above room temperature: change 1 LSB

– Verified with tests of TOFPET

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  • Temp. ¡(°C)

EOC ¡(bits) 0010111101 25 0011000000 50 0011000001 75 0011000001 100 0011000001 125 0011000001

simulations by Alberto Riccardi

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SLIDE 15

Mitglied der Helmholtz-Gemeinschaft

Temperature Stability of TDC

  • Conversion time in TDC, depending on temperature
  • Above room temperature: change 1 LSB

– Verified with tests of TOFPET

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  • Temp. ¡(°C)

EOC ¡(bits) 0010111101 25 0011000000 50 0011000001 75 0011000001 100 0011000001 125 0011000001

simulations by Alberto Riccardi

Finer simulation grid in room temp. regime

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Mitglied der Helmholtz-Gemeinschaft

Current work (comparator) and outlook

  • Concept for »hysteresis comparator« ready

– More robust for re-triggering on the falling edge – Current status: layout (learning) phase – Plan: finished until end of September

  • Starting in October with layout of Front-end

13

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SLIDE 17

Mitglied der Helmholtz-Gemeinschaft

PASTA Status Update

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Digital Part

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Mitglied der Helmholtz-Gemeinschaft

Meeting with TOFPET People (Lisbon)

  • Introduction into global controller and test benches
  • Lot‘s of small, technical questions
  • Structure of the digital part (esp. TDC Control)

– Room for optimizations

  • Structure not clear
  • Some solutions too complicated
  • Things done multiple times at different locations

– Leads to too much logic

  • Power
  • Area

15

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SLIDE 19

Mitglied der Helmholtz-Gemeinschaft

Meeting with TOFPET People (Lisbon)

  • Introduction into global controller and test benches
  • Lot‘s of small, technical questions
  • Structure of the digital part (esp. TDC Control)

– Room for optimizations

  • Structure not clear
  • Some solutions too complicated
  • Things done multiple times at different locations

– Leads to too much logic

  • Power
  • Area

15

Rewrite digital TDC!

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Mitglied der Helmholtz-Gemeinschaft

Some Conceptual Differences

  • Switch to different technology

– IBM 130 nm → UMC 110 nm

  • Time buffers move to global controller

– Saves connections

  • Hit validation in two ways

(delayed & synchronous)

  • More flexibility what to store

(t1-t3, t1-t2, test pulse)

  • Optimization in charging time
  • Refresh local instead global

– Capacitors back to reference level after inactivity

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U t t1 t3 UT UE t2

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Mitglied der Helmholtz-Gemeinschaft

Current Status of TDC Control

  • Basic concept is implemented

– Trigger, TAC selector, charge transfer and measurement, …

  • Details are missing
  • No SEU protection yet
  • Current status:

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TDC_CTRL v1

(incl. SEU, IBM)

TDC_CTRL v1

(incl. SEU, UMC)

TDC_CTRL v2

(current status, UMC)

Occupancy

(1.1 x 0.1 mm2)

84.8 % 37.0 %

no place & route yet

Cells 3155 2850 237 Power 1.57 mW/ch 1.78 mW/ch 0.03 mW/ch

@ 160 MHz

Estimate for final TDC Control: Save up to 80-90% in terms of power/occupancy

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Mitglied der Helmholtz-Gemeinschaft

Conclusion

  • Analogue part

– Front-end: concept ready, layout starts soon – TDC: switch to UMC complete, improved current stability

  • Digital part

– Switch to UMC: TDC CTRL (100%), GCTRL (0%) – Redesign started, current status promising

(power/occupancy down to ~10-20%)

  • Discussion needed

– Geometrical descisions

  • Channel pitch
  • Position of bonding pads

18

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Mitglied der Helmholtz-Gemeinschaft

Conclusion

  • Analogue part

– Front-end: concept ready, layout starts soon – TDC: switch to UMC complete, improved current stability

  • Digital part

– Switch to UMC: TDC CTRL (100%), GCTRL (0%) – Redesign started, current status promising

(power/occupancy down to ~10-20%)

  • Discussion needed

– Geometrical descisions

  • Channel pitch
  • Position of bonding pads

18

Thank you!

a.goerres@fz-juelich.de

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SLIDE 24

Mitglied der Helmholtz-Gemeinschaft

PASTA Status Update

19

Backup

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SLIDE 25

Mitglied der Helmholtz-Gemeinschaft

Hysteresis Comparator

  • Problem:

– Noise on the signal might lead to re-triggering

20

U t t1 t3 UT UE t2

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SLIDE 26

Mitglied der Helmholtz-Gemeinschaft

Hysteresis Comparator

  • Problem:

– Noise on the signal might lead to re-triggering – Additional time conversion

20

U t t1 t3 UT UE t2 t3 t2

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SLIDE 27

Mitglied der Helmholtz-Gemeinschaft

Hysteresis Comparator

  • Problem:

– Noise on the signal might lead to re-triggering – Additional time conversion

  • Solution:

– Different threshold levels for rising and falling edge – Re-triggering suppressed

20

U t t1 t3 UT UE t2 U t t3 UE_fe t2 UE_re t3 t2