[PPT] - ESA-ESTEC GSTP - Analog Silicon Compiler for Mixed-Signal ASICs PowerPoint Presentation

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ESA-ESTEC GSTP - Analog Silicon Compiler for Mixed-Signal ASICs

Analog Module Generator Software - AMGIE & MONDRIAAN

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 2

Outline

Introduction Objectives of WP1100 & WP1300 AMGIE Hierarchical Cell Design in AMGIE Low Power Optimization in AMGIE Radiation Tolerant Design Yield Optimization Mondriaan Conclusions

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 3

Introduction

Software development: WP1100 & WP1300 WP1100: Tool Requirement Analysis

ASICs/GVdP/WP1 report

WP1300: Software Implementation & Verification

Updated AMGIE software Mondriaan toolset Software User Manual

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 4

Objectives

ASTP4 project: Analog Module Generator (AMG)

Targeted to OPAMP level circuits :

automatic synthesis from specifications to layout

Both for novice and experienced designers

Extend and improve Analog Module Generator Reorient for expert designers

High-performance circuits: high-speed A/D converter Toolbox approach

Radiation tolerance

CSA-PSA circuit

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 5

Objectives cont’d

Translate Objectives into Requirements Tool Requirement Analysis (ASICs/GVdP/WP1)

Hierarchical cell design in AMGIE Low power optimization in AMGIE Radiation tolerant design Yield optimization Mondriaan

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 6

Outline

Introduction Objectives of WP1100 & WP1300 AMGIE Hierarchical Cell Design in AMGIE Low Power Optimization in AMGIE Radiation Tolerant Design Yield Optimization Mondriaan Conclusions

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 7

AMGIE: Definitions

Behaviour Specifications Structure

Sizes & Biasing Topology Selection Sizing Layout Generation

+

L1=1u

IB=10uA W1=10u

Vout := A(V+ - V-)

Av0 > 60dB GBW > 1 MHz ... +constraint specifications :

Schematic synthesis Geometry

W2=12u L2=1u L3=2u

Layout

W3=18u

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 8

AMGIE

Synthesis of OPAMP level complexity circuits Design methodology

Performance driven Hierarchical Design styles

Full custom Fixed

Cell Library

Custom topologies Fixed cells

Manual Synthesized

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 9

Outline

Introduction Objectives of WP1100 & WP1300 AMGIE Hierarchical Cell Design in AMGIE Low Power Optimization in AMGIE Radiation Tolerant Design Yield Optimization Mondriaan Conclusions

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 10

Hierarchical Cell Design in AMGIE

Implementation of stubs Design Controller Sizing & Optimization tool

Specification Translation tool

Layout tool

Layout Assembly tool

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 11

AMGIE: Design Flow

Top down Bottom up

cation Verifi- cation Verifi- Specifications at Level i + 1 Topology Selection Sizing and Optimization Extraction Layout Generation Layout at Level i + 1 Specifications at Level i Layout at Level i Redesign

Level i + 1 Level i

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 12

Design Controller

Old Design Flow (ASTP4 AMG) New Design Flow (GSTP AMGIE)

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 13

Hierarchical Cell Design: Sizing Tool

AMGIE sizing & optimization tool

Sizes of devices Biasing of devices

Hierarchical

Sizes of devices Biasing of devices Specifications of subcells

Specification translation S&O tool

Modified data handling

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 14

Hierarchical Cell Design: Layout Tool

LAYLA [Lampaert ‘99]

Analog place & route Direct performance driven, analog constraints

Symmetry Matching Parasitics

Optimized for typical analog circuits

OTA Opamp Comparator …

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 15

LAYLA: Miller_p circuit

Circuit level: fully functional layout Module level ?

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 16

Module Placement & Routing

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 17

Improved LAYLA

External Cells Floorplanning with soft cells Circuits & Modules:

OTAs Comparators CSA, PSA CSA-PSA Module A/D & D/A ?

Mondriaan

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 18

Outline

Introduction Objectives of WP1100 & WP1300 AMGIE Hierarchical Cell Design in AMGIE Low Power Optimization in AMGIE Radiation Tolerant Design Yield Optimization Mondriaan Conclusions

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 19

Low Power Optimization: Problem

Optimization algorithms

Global: Simulated Annealing Local: Hooke-Jeeves

highly constrained problems Optimization process

Black box Only cost trace is visible Final result can be investigated How to find good cost function parameters ?

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 20

Low Power Optimization: SQP

Added gradient based optimization algorithm

Sequential Quadratic Programming (SQP) Active constraint set

Buffer

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 21

Example: Power-Area Tradeoff

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 22

Low Power Optimization: Viewer

Optiman viewer

GUI Control center for optimization Displays state: current and best Optimization trace: history of process Internals optimization process

Gives control to

Experienced users Library developers

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 23

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 24

Outline

Introduction Objectives of WP1100 & WP1300 AMGIE Hierarchical Cell Design in AMGIE Low Power Optimization in AMGIE Radiation Tolerant Design Yield Optimization Mondriaan Conclusions

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 25

Radiation Tolerant Design

Problem description

M1 P1 P1

M1 P1

n NMOS VT

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 26

Radiation Tolerant Design

Counter irradiation effects by design

Layout measures Adapt sizing models: W & L, parasitics

Verify design

Commercial simulator Irradiation parameters

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 27

Edgeless Device – Gate All Around

Avoid the leakage path !

Source

Gate

Drain

? ?

eff eff

L W

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 28

Gate All Around Device

Drain Gate Source W1 W2 L

x x+dx

          = =

eff eff eff eff

L W W W W W L W 8 exp ) ln( 8

1 2 1 2

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 29

Device Generator

CADENCE & LAYLA

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 30

Radiation Tolerant Design: Sizing

Margins

VT Shifts Leakage currents

Gate all around device

Use geometric model W & L Parasitics: AS, AD, PS, PD, NRS, NRD, …

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 31

KULeuven PDFE Example

1.1mm 550um

Rf CSA Diff INT

GAA

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 32

Radiation Tolerant Design: Verification

Verification

Commercial simulators offer simulation of irradiation effects Hspice has been integrated in the verification tool 2 examples:

NMOS transistor Simulated KULeuven PDFE

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 33

NMOS Transistor: Subthreshold Slope

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 34

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 35

Outline

Introduction Objectives of WP1100 & WP1300 AMGIE Hierarchical Cell Design in AMGIE Low Power Optimization in AMGIE Radiation Tolerant Design Yield Optimization Mondriaan Conclusions

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 36

Yield: Problem Description

Nominal Design Manufacturing tolerance

Inter-die

Wafer batches Different wafers in one batch Modeled through spice parameter 6σ intervals

Intra-die

Same devices, unequal parameters Mismatch

Yield

Some circuits are not within spec

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 37

Inter-die Yield Optimization

simultaneous sizing for nominal performance and

yield/robustness

automatically derived sensitivities to calculate yield/Cpk during

sizing

computational plan to calculate nominal point all design equations & variables SPICE-like computational plan computational plan to calculate sensitivities input set = (W,L,θ)

DONALD

input set = (θ,L,Vnode,Ibranch) symbolic derivatives all DONALD variables

θ L Ibranch Vnode

j , i y ,

S i

j ∀

θ

executable executable

by propagation

f variances on

symbolic model

Inter-die

[Debyser ICCAD98]

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 38

Inter-die Yield Optimization: Example

Monte Carlo example : current-buffer OTA

random starting point nominal/yield/Cpk optimization Monte-Carlo verification

results after optimization

GBW>100MHz Av0>60dB PM>60deg OR>3.0V Voff<5mV Itot<3.0mA 165 78.0 60.2 3.1 4.8 2.6 172 78.1 63.6 3.27 3.5 2.6 23.1 1.68 0.2 0.05 0.14 0.4 21.4 1.74 0.4 0.058 0.7 0.56

y y

y

σ

y

σ

yield model

specs CPU times

Monte Carlo yield model

ptimization

2h20’ (300s) 10” 2h15’

Μ1a Μ1b Μ7 Μ6 CL Μ3b Μ2b Μ2a Μ3a Μ5a Μ4a Μ5b Μ4b Vbias1 Vbias2 Vbias3 V+ V- Vout

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 39

Example: Results

1 2

1 : pdf distributions without yield/Cpk

(nominal only)

2 : pdf distributions with yield/Cpk

(nominal + yield)

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 40

Intra-die Yield: Mismatch

A/D converter: INL specification MOS mismatch model [Pelgrom JSSC’89]: variance on

VT ß

Sizing model includes mismatch yield through equations Mismatch verification

2 2 2 2 2 2 2 2

D S WL A D S WL A

Vt Vt Vt β β β β β β

σ σ

∆ ∆ ∆ ∆

+ = + =

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 41

Mismatch verification: Comparator

vin+ vin- vout+ vout- φ1 φ2 φ1 φ1 φ1 M4a M4b M2a M2b M3a M3b Mbias M5a M5b M1a M1b

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 42

Transient Simulation

t0

∆Vout

t0 t1 t2

utput voltage at

a fixed time point

[VdPlas ICECS99]

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 43

Result Monte Carlo Simulation

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 44

Outline

Introduction Objectives of WP1100 & WP1300 AMGIE Hierarchical Cell Design in AMGIE Low Power Optimization in AMGIE Radiation Tolerant Design Yield Optimization Mondriaan Conclusions

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 45

Mondriaan: Introduction

Often used analog signal processing architectures:

generation, propagation, multiplication

# output # output # output # input

1 A B C 1 A B C 1 A B C 1 A B C

# input

[VdPlas CICC98]

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 46

Examples

A/D converter D/A converter

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 47

Generation of Regular Layout Structures

Hierarchy

changes lead to a complete redesign of the cell hierarchy exceptions difficult to handle

Stretch & Tile [Neff]

☺ extremely fast generation all connectivity by abutment large setup time

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 48

Mondriaan Features

Regular array of cells Use abutment for power, biasing, … Bus & Channel routing for extra connectivity

Y bus routing connects to cells X channel routing connects to Y routing

Mondriaan Flow Bus and Tree device generators

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 49

Mondriaan: Layout Model

Matrix of master cells (master1,master2,...) Optional column spacer cells (sp1, sp2)

sp1

sp1 master1 sp2 master2 master3

sp1 sp1

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 50

Mondriaan: Layout Model

Symbolic view: X & Y channel routing

contact area Y X-Y

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 51

Mondriaan Flow

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 52

Example: 4-bit Current Source Array

1 current source == 4 MOS transistors symmetric placement Floorplan

1A 2A 0A 3A 5A 4A 7A 6A 9A 8A 10A 11A 12A 13A 14A

2B

1B 0B 0C 1C 2C 0D 1D 2D

==

3B 8B 7B 12B 13B 14B 11B 9B 10B

5B

4B 6B 3C 12C 14C 13C

11C

5C 4C 6C 8C 9C 7C 10C 6D 8D 9D 7D 3D 12D 14D 13D 10D 11D

5D

4D dummies j jA jB jC jD dummies

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 53

Layout of 4-bit Array

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 54

Bus and Tree Generators

Tree Buses

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 55

Bus Generators

N-to-N connections: 6 types Signal distribution, clock distribution, …

(a) (b) (c)

routing2 via routing1 routing2 via routing1

(d) (e) (f)

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 56

Tree Generators

1-to-N connections: 3 types Clock distribution, biasing, power, ground, …

pitch width height growstep=2 startwidth routing layer1 routing layer2 via layer pitch width height grow-ratio width pitch height pitch2

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 57

CURRENT SOURCE ARRAY SWATCH ARRAY FULL DECODER

DIGITAL CLOCK DRIVER ANALOG CLOCK DRIVER

4.1x3.2mm

14-bit D/A Converter

[VdPlas DAC00]

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 58

Outline

Introduction Objectives of WP1100 & WP1300 AMGIE Hierarchical Cell Design in AMGIE Low Power Optimization in AMGIE Radiation Tolerant Design Yield Optimization Mondriaan Conclusions

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 59

Conclusions

Improved AMGIE

Hierarchical cell design Low power optimization Yield optimization

Radiation tolerance

GAA Verification

Mondriaan

Layout for A/D converters

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Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 60

Publications

G. Van der Plas, J. Vandenbussche, G. Gielen and W. Sansen, "Mondriaan: a

Tool for Automated Layout Synthesis of Array-type Analog Blocks", Proc. on the IEEE 1998 Custom Integrated Circuits Conference (CICC), pp. 485-488, California, May 1998.

G. Debyser, G. Gielen, “Efficient analog circuit synthesis with simultaneous yield

and robustness optimization”, proceedings ACM/IEEE International Conference

n Computer-Aided Design (ICCAD), pp. 308-311, November 1998.
G. Van der Plas, J. Vandenbussche, W. Verhaegen, G. Gielen and W.Sansen,

"Statistical Behavioral Modeling for A/D Converters", IEEE 1999 International Conference on Electronics, Circuits and Systems (ICECS), pp. 1713-1716, Cyprus, September 1999.

G. Van der Plas, J. Vandenbussche, W. Daems, A. Van Den Bosch, G. Gielen, M.

Steyaert, W. Sansen, "Systematic design of a 14-bit 150-MS/s CMOS Current- Steering D/A Converter", in Design Automation Conference (DAC), pp. 452-457, Los Angelos, USA, June 5-9, 2000.