ESA-ESTEC GSTP - Analog Silicon Compiler for Mixed-Signal ASICs - PowerPoint PPT Presentation

ESA-ESTEC GSTP - Analog Silicon Compiler for Mixed-Signal ASICs Analog Module Generator Software - AMGIE & MONDRIAAN

Outline � Introduction � Objectives of WP1100 & WP1300 � AMGIE � Hierarchical Cell Design in AMGIE � Low Power Optimization in AMGIE � Radiation Tolerant Design � Yield Optimization � Mondriaan � Conclusions Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 2

Introduction � Software development: WP1100 & WP1300 � WP1100: Tool Requirement Analysis � ASICs/GVdP/WP1 report � WP1300: Software Implementation & Verification � Updated AMGIE software � Mondriaan toolset � Software User Manual Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 3

Objectives � ASTP4 project: Analog Module Generator (AMG) � Targeted to OPAMP level circuits : automatic synthesis from specifications to layout � Both for novice and experienced designers � Extend and improve Analog Module Generator � Reorient for expert designers � High-performance circuits: high-speed A/D converter � Toolbox approach � Radiation tolerance � CSA-PSA circuit Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 4

Objectives cont’d � Translate Objectives into Requirements � Tool Requirement Analysis (ASICs/GVdP/WP1) � Hierarchical cell design in AMGIE � Low power optimization in AMGIE � Radiation tolerant design � Yield optimization � Mondriaan Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 5

Outline � Introduction � Objectives of WP1100 & WP1300 � AMGIE � Hierarchical Cell Design in AMGIE � Low Power Optimization in AMGIE � Radiation Tolerant Design � Yield Optimization � Mondriaan � Conclusions Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 6

AMGIE: Definitions Behaviour + - Structure Vout := A(V+ - V-) +constraint specifications : Av0 > 60dB GBW > 1 MHz ... Specifications Sizes & Biasing IB=10uA Geometry Topology W1=10u L1=1u Selection W2=12u L2=1u W3=18u L3=2u Sizing Schematic synthesis Layout Generation Layout Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 7

AMGIE � Synthesis of OPAMP level complexity circuits � Design methodology � Performance driven � Hierarchical � Design styles � Full custom � Fixed � Cell Library � Custom topologies � Fixed cells � Manual � Synthesized Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 8

Outline � Introduction � Objectives of WP1100 & WP1300 � AMGIE � Hierarchical Cell Design in AMGIE � Low Power Optimization in AMGIE � Radiation Tolerant Design � Yield Optimization � Mondriaan � Conclusions Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 9

Hierarchical Cell Design in AMGIE � Implementation of stubs � Design Controller � Sizing & Optimization tool � Specification Translation tool � Layout tool � Layout Assembly tool Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 10

AMGIE: Design Flow Specifications at Level i Layout at Level i � Top down � Bottom up Level i Topology Verifi- Selection cation Redesign Sizing and Optimization Extraction Verifi- Layout cation Generation Level i + 1 Specifications at Level i + 1 Layout at Level i + 1 Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 11

Design Controller Old Design Flow (ASTP4 AMG) New Design Flow (GSTP AMGIE) Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 12

Hierarchical Cell Design: Sizing Tool � AMGIE sizing & optimization tool � Sizes of devices � Biasing of devices � Hierarchical � Sizes of devices � Biasing of devices � Specifications of subcells � Specification translation � S&O tool � Modified data handling Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 13

Hierarchical Cell Design: Layout Tool � LAYLA [Lampaert ‘99] � Analog place & route � Direct performance driven, analog constraints � Symmetry � Matching � Parasitics � Optimized for typical analog circuits � OTA � Opamp � Comparator � … Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 14

LAYLA: Miller_p circuit � Circuit level: fully functional layout � Module level ? Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 15

Module Placement & Routing Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 16

Improved LAYLA � External Cells � Floorplanning with soft cells � Circuits & Modules: � OTAs � Comparators � CSA, PSA � CSA-PSA Module � A/D & D/A ? � Mondriaan Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 17

Outline � Introduction � Objectives of WP1100 & WP1300 � AMGIE � Hierarchical Cell Design in AMGIE � Low Power Optimization in AMGIE � Radiation Tolerant Design � Yield Optimization � Mondriaan � Conclusions Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 18

Low Power Optimization: Problem � Optimization algorithms � Global: Simulated Annealing � Local: Hooke-Jeeves � highly constrained problems � Optimization process � Black box � Only cost trace is visible � Final result can be investigated � How to find good cost function parameters ? Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 19

Low Power Optimization: SQP � Added gradient based optimization algorithm � Sequential Quadratic Programming (SQP) � Active constraint set Buffer Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 20

Example: Power-Area Tradeoff Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 21

Low Power Optimization: Viewer � Optiman viewer � GUI � Control center for optimization � Displays state: current and best � Optimization trace: history of process � Internals optimization process � Gives control to � Experienced users � Library developers Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 22

Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 23

Outline � Introduction � Objectives of WP1100 & WP1300 � AMGIE � Hierarchical Cell Design in AMGIE � Low Power Optimization in AMGIE � Radiation Tolerant Design � Yield Optimization � Mondriaan � Conclusions Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 24

Radiation Tolerant Design � Problem description P1 P1 V T M1 M1 NMOS n P1 Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 25

Radiation Tolerant Design � Counter irradiation effects by design � Layout measures � Adapt sizing models: W & L, parasitics � Verify design � Commercial simulator � Irradiation parameters Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 26

Edgeless Device – Gate All Around � Avoid the leakage path ! Drain Gate ? W eff Source L ? eff Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 27

Gate All Around Device Drain x x+dx W 8 = eff Gate W L ln( ) 2 eff W 1 Source     W 8 =   2 exp W   W eff 1  L  eff W1 L W2 Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 28

Device Generator CADENCE & LAYLA Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 29

Radiation Tolerant Design: Sizing � Margins � V T Shifts � Leakage currents � Gate all around device � Use geometric model � W & L � Parasitics: AS, AD, PS, PD, NRS, NRD, … Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 30

KULeuven PDFE Example GAA 550um R f CSA Diff INT 1.1mm Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 31

Radiation Tolerant Design: Verification � Verification � Commercial simulators offer simulation of irradiation effects � Hspice has been integrated in the verification tool � 2 examples: � NMOS transistor � Simulated KULeuven PDFE Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 32

NMOS Transistor: Subthreshold Slope Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 33

Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 34

Outline � Introduction � Objectives of WP1100 & WP1300 � AMGIE � Hierarchical Cell Design in AMGIE � Low Power Optimization in AMGIE � Radiation Tolerant Design � Yield Optimization � Mondriaan � Conclusions Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 35

Yield: Problem Description � Nominal Design � Manufacturing tolerance � Inter-die � Wafer batches � Different wafers in one batch � Modeled through spice parameter 6 σ intervals � Intra-die � Same devices, unequal parameters � Mismatch � Yield � Some circuits are not within spec Final presentation – ESA-ESTEC 7/3/2001 Geert Van der Plas 36