SLIDE 1
Conventional Clock Distribution
Grid H Tree Routed Tree Gclk
- Central distribution relies on global matching
An Active GHz Clock Network Using Distributed PLLs Vadim Gutnik and - - PowerPoint PPT Presentation
An Active GHz Clock Network Using Distributed PLLs Vadim Gutnik and - - PowerPoint PPT Presentation
An Active GHz Clock Network Using Distributed PLLs Vadim Gutnik and Anantha Chandrakasan Microsystems Technology Lab Massachusetts Institute of Technology Cambridge, MA Conventional Clock Distribution H Tree Gclk Routed Tree Grid
SLIDE 2
SLIDE 3
Sources of Clock Uncertainty
- Systematic: passive compensation
- Random and dynamic: active compensation
Source Buffers Wires Load
SLIDE 4
Distributed Clock Generation
- Synchronized clock generated at multiple points
Oscillators Phase Detectors GCLK
SLIDE 5
Why Symmetric PLLs?
Σ
PD
Σ
PD
Σ
PD
Ref Σ
PD
Σ
PD
Σ
PD
Ref
log(ω)
Noise transfer function
1 2
1 2
SLIDE 6
How Many Tiles?
10 20 30 40 50
1 4 9 16 25 36 49 64 Number of Tiles
Clock skew (ps)
Total Skew Internal Skew Boundary Skew 2cm x 2cm 1GHz clock 0.25 µm
SLIDE 7
Modelock
1 2 3 4 1 2 4 3
[Pratt 95]
Next Phase = current phase - average phase error
SLIDE 8
Is Modelock Avoidable?
1 3 2 1 3 2 1 3 2
1 2 θ
1 2 3
1 2 θ
1 3 2 1 3 2 1 3 2
Linear phase detector: mode lock Desired phase detector
SLIDE 9
Nonlinear Error Summing
- n from geometry, θcrit = 360/n
- Nonlinearity makes modelocked states unstable
Phase-detector output current Phase difference θcrit
SLIDE 10
Phase Detector - phase
Out2 Out1 In1 In2
In1 In2 P1 P2 Out1 Out2
Out1-Out2 phase
SLIDE 11
Phase Detector - frequency
Out1-Out2 frequency
In1 In2 P1 P2 Out1 Out2
Out2 Out1 In1 In2
SLIDE 12
Small-Signal Stability
s-plane σ jω
+ + + +
PD PD PD PD
Reference
PD
log(ω)
Noise transfer function
u A A A I
1 1 2 1
) h( )] h( [ s s s
−
− = Φ
SLIDE 13
Loop Filter
In+ In- Iout In+ In- Iout
Pbias Nbias
SLIDE 14
Oscillator
Input
- NMOS-load differential ring oscillator insensitive to
supply noise
SLIDE 15
Large-Signal Acquisition
0.9 0.95 1 1.05 1.1 1 2 3 4 5 6 7 8 9 10 Simulation time (microseconds) Clock Period (nanoseconds)
Reference
SLIDE 16
Full System Hspice Simulation
- 16 oscillator network small-signal stable
0.99 1 1.01 1.02 1 2 3 4 Simulation Time (microseconds) Clock Period (nanoseconds)
SLIDE 17
Results
- 2mm chip. 0.35 µm, single poly triple metal CMOS
- 16 oscillators, each 40µm x 40µm
- 24 phase detectors, each 20µm x 40µm
- Total power: 450mW at 3V, 1.3GHz
- Jitter < 30ps
SLIDE 18
Conclusions
- Random and time-varying mismatch limit centralized
clock distribution
- Distributed generation enables shorter distribution
- Stable multiple-oscillator PLL demonstrated
SLIDE 19