SLIDE 1
A2:$Analog$Malicious$Hardware$
Kaiyuan$Yang,$Ma8hew$Hicks,$Qing$Dong,$Todd$Aus>n,$and$Dennis$ Sylvester$ $ University$of$Michigan$
Founda>ons$are$important$
2$
A2:$Analog$Malicious$Hardware$ - - PowerPoint PPT Presentation
A2:$Analog$Malicious$Hardware$ - - PowerPoint PPT Presentation
A2:$Analog$Malicious$Hardware$ Kaiyuan$Yang,$Ma8hew$Hicks,$Qing$Dong,$Todd$Aus>n,$and$Dennis$ Sylvester$ $ University$of$Michigan$ Founda>ons$are$important$ 2$ Applica5ons) Opera5ng)System) Weakened$hardware$ Hypervisor)
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SLIDE 3
Weakened$hardware$ weakens$the$en>re$ system$
Untrusted) Hardware) Firmware) Hypervisor) Opera5ng)System) Applica5ons)
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SoIware$security$success$forces$a8ackers$to$ lower$layers$
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SoIware$security$success$forces$a8ackers$to$ lower$layers$
rootkits malicious hypervisors bootkits malicious hardware
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Visual)Inspec5on) Side)Channels) ) )
catches$a8acks$that$are$large$ because$they$use$addi>onal$ logic$to$hide$from$dynamic$ analysis$
Dynamic)+)Sta5c) Analysis) ) )
catches$a8acks$that$are$small$ because$they$are$always$on$
)
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Challenge:$construct$an$a8ack$that$is$stealthy$ and$small$$
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Challenge:$construct$an$a8ack$that$is$stealthy$ and$small$$
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Two$threats,$we$focus$on$the$stage$that$restricts$ the$a8acker$the$most$
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Foundry$ GDSII$ BackTend$house$ netlist$
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We$leverage$analog$behavior$to$construct$an$ a8ack$that$is$stealthy$and$small$$
- n_every(RBACE)/do/
///if(count/==/12345)/then/ //////do_attack()/ ///else/ //////count/=/count/+/1/ done/
RBACE$=$rare,$but$a8acker$controllable$event$
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We$leverage$analog$behavior$to$construct$an$ a8ack$that$is$stealthy$and$small$$
- n_every(RBACE)/do/
///if(count/==/12345)/then/ //////do_attack()/ ///else/ //////count/=/count/+/1/ done/
RBACE$=$rare,$but$a8acker$controllable$event$ RBACE)=)vic5m)wire$
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An$ideal$analog$trigger$
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An$ideal$analog$trigger$
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An$ideal$analog$trigger$
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An$ideal$analog$trigger$
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SLIDE 16
Challenge:$small$capacitors$charge$quickly,$ large$capacitors$induce$current$spikes$
current$ value$ current$ charge$
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Challenge:$small$capacitors$charge$quickly,$ large$capacitors$induce$current$spikes$
current$ value$ current$ charge$
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SLIDE 18
Challenge:$small$capacitors$charge$quickly,$ large$capacitors$induce$current$spikes$
current$ value$ current$ charge$
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SLIDE 19
Solu5on:$charge$sharing$
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SLIDE 20
Crea>ng$an$analog$trigger$using$gated$charge$ sharing$
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VDD Cunit Cmain Victim Wire Victim Wire
Time
VDD
Cap* Voltages
Cunit Cmain
1
Victim Wire
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Crea>ng$an$analog$trigger$using$gated$charge$ sharing$
21$
Time
VDD
Victim Wire Cap. Voltages
Cunit Cmain
1
VDD Cunit Cmain Victim Wire Victim Wire
SLIDE 22
Crea>ng$an$analog$trigger$using$gated$charge$ sharing$
22$
Time
VDD
Victim Wire Cap. Voltages
Cunit Cmain
1
VDD Cunit Cmain Victim Wire Victim Wire
SLIDE 23
Crea>ng$an$analog$trigger$using$gated$charge$ sharing$
23$
Time
VDD
Cap* Voltages
Cunit Cmain
Victim Wire
1
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Crea>ng$a$privilege$escala>on$a8ack$
*Our$analog$trigger$is$a8ack$agnos>c$
Inverted)reset) Posi5ve)reset)
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A2)
Vic5m)Wire$ A2)Trigger$
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Implan>ng$A2$into$an$exis>ng$chip$layout$
A2 Trigger
20%$to$30%$
- f$chip$area$
is$unused)
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Other$challenges$in$the$paper$
- Analog$circuit$design$process$
- Finding$a$suitable$vic>m$wire$
- Finding$the$flipTflop$to$a8ack$
- Building$mul>Tstage$a8acks$
- Wri>ng$trigger$ac>va>on$code$
- Covertly$tes>ng$for$a8ack$success$
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We$had$to$build$A2$to$know$it$worked$
Main Memory 128KB SRAM OR1200 Core
I$
Testing Structure Scan chain
IO Drivers and Pads
CLK
1.4 mm 1.5 mm 6.4 µm 2 µm
A2 Trigger
Metal 3 Metal 2 Via 28$
SLIDE 29
We$ac>vate$A2$in$real$hardware$using$only$ user$mode$code$
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SLIDE 30
A2$is$hidden$from$postTfab$tes>ng$
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.0002$for$divisionT heavy$benchmark$
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A8ackers$can$reliably$model$their$a8acks$
Where$is$this$in$real$hardware?$ Every$chip$is$different!$
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A8ackers$can$reliably$model$their$a8acks$
The$a8ack$is$not$well$hidden$ from$dynamic$analysis$(tes>ng)$
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SLIDE 33
A8ackers$can$reliably$model$their$a8acks$
The$a8ack$is$impossible$to$trigger$
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A8ackers$can$reliably$model$their$a8acks$
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More$experiments$in$the$paper$
- Comparison$of$different$standard$cell$sizes$and$out$a8ack$
- Distribu>on$of$trigger$>mes$
- Distribu>on$of$reten>on$>mes$
- Effect$of$voltage$on$cycles$to$trigger$
- Effect$of$temperature$on$cycles$to$trigger$
- Effect$of$temperature$on$reten>on$>me$
- Power$of$benchmarks$and$a8ack$programs$
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CrossTdomain$a8acks$are$stealthy$and$ controllable$
- A2$spans$the$analog$and$digital$domains$
- A2$is$controllable$
- A2$is$stealthy$
– complex$and$unlikely$trigger$sequence$ – a$single$cell$
- Currently,$only$detectable$postTfabrica>on$
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detec5on)
plus$
protec5on$
We$need$to$try$something$ different:)
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Fabricator) Popular$offshore$corp.$$ Interface) GDSII$ Turnaround)5me) 3$months$ Added)5me)to)project) 1$year$ Area) 1.5mm$x$1.5mm$ Core) 330um$x$550um$ Memory) 1145um$x$765um$ Process) 65nm$ Number)of)chips) 100$ Cost) $5k$to$$10k$per$1mm2$ Other)costs) packaging$
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