A mixed-signal ic for managing power in 5G applications IPSOC 2018 - - PowerPoint PPT Presentation

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a mixed signal ic for managing power in 5g applications
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A mixed-signal ic for managing power in 5G applications IPSOC 2018 - - PowerPoint PPT Presentation

Apr 10, 2023 207 likes •365 views

A mixed-signal ic for managing power in 5G applications IPSOC 2018 Introduction Architecture of mixed-signal ics in handsets IPSOC 2018 2 MODEM architecture Protocol stack (RTOS) Transceiver soup letter TDMA, OFDM, CDMA

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SLIDE 1

A mixed-signal ic for managing power in 5G applications

IPSOC 2018

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SLIDE 2

IPSOC 2018 2

Introduction

  • Architecture of mixed-signal ic’s in handsets
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SLIDE 3

IPSOC 2018 3

MODEM architecture

  • Protocol stack (RTOS)
  • Transceiver soup letter TDMA, OFDM, CDMA
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IPSOC 2018 4

OFDM subcarriers interference

Frequency Time

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IPSOC 2018 5

Power amplifier

  • “Unreasonable” requirements on RF transistor
  • Large Peak to Average Power ratio
  • Hard to predict subcarrier interference
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IPSOC 2018 6

OFDM subcarriers interference

  • Temptation to use math (from dsplog.com)
  • PAPR is the maximum full scale signal power

divided by the expected (average) power

– PAPR of a single sine tone = 2 – PAPR of a single complex sinusoidal tone = 1 – Maximum expected PAPR from OFDM waveform with k subcarriers = k

  • Important result
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IPSOC 2018 7

PAPR mitigation approaches

  • Do nothing
  • Allow for worst-case high peak power
  • Drive signal saturation probability
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SLIDE 8

IPSOC 2018 8

Ideal high PAPR solution

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SLIDE 9

IPSOC 2018 9

Mixed-signal circuit to the rescue

  • Many approaches to PAPR mitigation include

“detectors”

  • Power supply compliance has to be just 10%
  • Lead us not into temptation…

Carrier frequency is GHz!

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SLIDE 10

IPSOC 2018 10

Open loop drive (Elastic Backoff™)

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IPSOC 2018 11

Charge-pump circuit (Dickson)

  • Each stage boosted by switching voltage
  • Simulation typically overestimates efficiency

– 50% with integrated capacitors – > 80% with external capacitors

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IPSOC 2018 12

Actual charge-pump circuit

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IPSOC 2018 13

Charge-pump behavior

0ns 4ns 8ns 12ns 16ns 20ns 24ns 28ns 32ns 36ns 0.0V 0.4V 0.8V 1.2V 1.6V 2.0V 2.4V 2.8V 3.2V 3.6V 4.0V

  • 0.4V

0.0V 0.4V 0.8V 1.2V 1.6V 2.0V 2.4V 2.8V 3.2V 3.6V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V 6.0V 6.5V 7.0V

  • 14mA
  • 12mA
  • 10mA
  • 8mA
  • 6mA
  • 4mA
  • 2mA

0mA 2mA 4mA V(phia) V(phib) V(charge-pump:phia_n) V(charge-pump:phib_n) V(out) I(Vdda)

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IPSOC 2018 14

Load-line

  • Charge-pump is able to supply any current at a

fixed voltage (up to the load maximum)

  • This is a “voltage” source
  • Linear regulation with a switching behavior
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SLIDE 15

IPSOC 2018 15

Conclusions

  • Complex analog/mixed-signal integration, but

PV circuit blocks

  • Saves 30% power consumption with easy to

integrate components

  • Semiconductor does not know if it’s analog or

digital!!!