A Low-Voltage Log-Domain Integrator Using MOSFET in Weak Inversion - PowerPoint PPT Presentation

A Low-Voltage Log-Domain Integrator Using MOSFET in Weak Inversion Lida Ramezani Electrical & Computer Engineering Dept., Ryerson University, lramezan@ee.ryerson.ca PATMOS2010 1

Outline Introduction 1. Main idea and concepts 2. 2-1 MOSFET in Weak inversion or sub-threshold 2-2 Transient frequency of MOSFET in sub-threshold 2-3 Trans-linear principle 2-4 A CMOS translinear loop 2-5 Companding theory 2-6 Log companding integrators Circuit design 3. 3-1 MOSFET realization of first order filter 3-2 Log domain integrator circuit 3-3 Integrator circuit specifications CADENCE-Spectre Simulation results 4. 4-1 Transient and frequency response of integrator 4-2 Cutoff frequency tuning using variable integrating capacitor 4-3 Cut off frequency Tuning using variable bias current Summary and Conclusions 5. References PATMOS2010 2

1. Introduction 1.1 Low power techniques 1.2 Linear circuit constraints in low-power, low-voltage, high frequency and large dynamic range design 1.3 Externally linear, internally Nonlinear circuit design PATMOS2010 3

1.1 Low-power techniques Low power integrated circuits are required in portable systems. � Analog filters are among circuits used in these systems. Integrators are building blocks in cascaded filters. PATMOS2010 4

1.2 Linear circuit constraints in low-power, low-voltage, high frequency and large dynamic range design Low voltage linear circuits suffer from dynamic range limitations: � � Input voltage swing � The input signal should be several times less than bias level to reduce harmonic distortion. At the same time, input noise level should be kept as low as possible. � For higher dynamic range, large bias level are needed that causes large power consumption. There are several linearization techniques such as: � � Source degeneration, � Nonlinear term cancellation � Class AB implementation In these linearization methods several transistors are added to the circuit. � Each transistor adds several parasitic capacitors and causes more limited bandwidth. For high-frequency and low-power circuit design, simple circuits with less � count of transistors are preferred. PATMOS2010 5

1.3 Externally linear, internally Nonlinear (ELIN) circuit design • Nonlinear circuits have a larger input range with less bias levels and lower supply voltage. • With the lack of linearization transistors, simple circuits with less count of transistors and less power consumption are used. Also, simple nonlinear circuits have less count of parasitic capacitors and are suitable for high frequencies. •Log companding filters are kind of externally linear internally nonlinear ELIN circuits. In this presentation a new ELIN integrator (first order filter) is introduced. PATMOS2010 6

2. Main Idea and related 2. Main Idea and related Concepts Concepts 2-1 MOSFET in Weak inversion or sub-threshold 2-2 Transient frequency of MOSFET in sub-threshold 2-3 Trans-linear principle 2-4 A CMOS translinear loop 2-5 Companding theory 2-6 Log companding integrators PATMOS2010 7

Main idea � The main idea is design of a simple ELIN integrator in which companding method is used to improve dynamic range . � MOSFET in weak inversion is used as compressor and expander. � Transistor in sub-threshold works with low gate-source voltage i.e. less than threshold voltage, therefore a low supply voltage of 500mv is used. � Transistor in weak inversion has the highest Gm/Ibias ratio. PATMOS2010 8

2.1 MOSFET in sub-threshold or Weak inversion 2.1 MOSFET in sub-threshold or Weak inversion � When the gate source voltage of a MOS transistor is less than threshold voltage but high enough to create depletion region at the surface of silicon, the device operates in weak inversion . This is called sub-threshold region and MOS has exponential voltage- current characteristics [3]. ⎛ ⎞ ≤ ≤ ⇒ ≤ ≤ ⎛ ⎞ ⎛ ⎞ − − 0 0 V V I I V V V = − ⎜ ⎟ GS th D Spec . ⎜ G S th ⎟ ⎜ D S ⎟ I I ex p 1 ex p ⎜ ⎟ D S p ec . ⎝ ⎠ ⎝ ⎠ n V ⎝ V ⎠ C T T = + js ฀ 1 1.5 n ⎛ − ⎞ C V V > ⇒ ox ฀ ⎜ ⎟ G S th V 3 V I I ex p D S T D S p ec . β ⎝ ⎠ 2 n V ฀ I 2 n V T Spec . T ⎛ ⎞ w I β = μ = + ⎜ ⎟ D c V V n V ln ⎜ ⎟ n ox G S th T l I ⎝ ⎠ sp ec . PATMOS2010 9

2.2 Transient frequency of MOSFET in weak-inversion � Transient frequency of MOSFET in weak-inversion is proportional to its bias current. Smaller transistors have higher transient frequency. g I = ⇒ = m D f f π π T T 2 C 2 V wlC g T js ∂ I I = = D D g ∂ m V nV GS T C = + js n 1 C ox = + + ฀ C C C C C g gb gs gd gb ⎛ ⎞ ⎛ ⎞ C C C = = ⎜ ⎟ js ox js ⎜ ⎟ C wl wl ⎜ ⎟ + gb ⎝ ⎠ C C n ⎝ ⎠ js ox PATMOS2010 10

2.3 Trans-linear principle 2.3 Trans-linear principle � A trans-linear element is a physical device whose trans- conductance gain and current through the device are linearly related. MOSFET in sub-threshold is a trans-linear elements . � A closed loop containing equal number of oppositely connected trans-linear elements is called a trans-linear loop . � According to trans-linear principle [2], in a trans-linear loop, the product of the current densities in the elements connected in clockwise (CW) direction is equal to the corresponding product for elements connected in the counter clockwise (CCW) direction. Π = Π I I n m ∈ ∈ n CW m CCW PATMOS2010 11

2.4 A trans-linear loop with MOSFET in weak inversion 2.4 A trans-linear loop with MOSFET in weak inversion A CMOS trans-linear loop is shown in Fig.2. All transistors are biased in � weak-inversion. ⎛ ⎞ I ( ) = + ⎜ ⎟ D V nV ln V ⎜ ⎟ GS T th I ⎝ ⎠ spec . < < 0 V V GS th < < 0 I I D spec . + = + V V V V GS 1 GS 2 GS 3 GS 4 ⇒ × = × I I I I 1 2 3 4 D D D D Fig.2: A CMOS translinear loop PATMOS2010 12

2.5 Companding method 2.5 Companding method � In companding method, compressor and expander circuits are used. � The c ompressor circuit compresses the dynamic range of the input; it amplifies weak signals so that they can be transmitted with noise immunity. � The expander circuit expands the dynamic range; it reduces the amplitude of the amplified signals and thus of the noise picked up during transmission. � Companding can be used in log domain filters to enable supply voltage reduction without signal to noise ratio degeneration [6]. PATMOS2010 13

Block diagram of a log companding integrator = ˆ( ) x t k ln ( ) x t ∫ = = ' ˆ ( ) ( ( )) ˆ ˆ ( ) y t f x t k x t dt = '' y t ˆ ( ) y t ( ) k e Log compressor Antilog expander PATMOS2010 14

A log companding integrator circuit Using MOSFET in sub-threshold × = × i i i i A log companding integrator, is 1 2 3 4 D D D D ( ) ( ) ( ) + × = + × i ( ) t I I I i ( ) t i ( ) t composed of a trans-linear loop and an in 1 2 3 C out integrating capacitor. ⎛ ⎞ i ( ) t = = + ⎜ ⎟ out v ( ) t v ( ) t nV ln V ⎜ ( ) ⎟ C gs 4 T th I w l ⎝ ⎠ t 4 dv t ( ) CnV di ( ) t = = c T out i ( ) t C C dt i ( ) t dt out ⎛ ⎞ CnV di ( ) t ( ) ( ) + × = + × ⎜ out ⎟ T i ( ) t I I I i ( ) t in 1 2 3 out ⎝ ⎠ i ( ) t dt out CnV di ( ) t = ( I ) + + × out 2 T i ( ) t i ( ) t I out in 1 I dt I 3 3 ( ) I I ( ) i s = = 2 3 out H s ( ) ( ) ( ) + ω i ( ) s 1 s in 0 I ω = 3 Fig.3: Log domain integrator using 0 CnV T MOSFET in sub-threshold PATMOS2010 15

3. Circuit design 3. Circuit design 3.1 Imp 3.1 Implemen ementation tion of of a CM a CMOS Log domain int OS Log domain integrator grator 3.2 In 3.2 Integrator tegrator cir circuit specificat cuit specification ons PATMOS2010 16

3.1 Implementation of a CMOS Log domain integrator circuit 3.1 Implementation of a CMOS Log domain integrator circuit PATMOS2010 17

3.2 Integrator circuit specifications 3.2 Integrator circuit specifications para parame meter ter value value M3, M7, M2, M6 (w/l)=480n/130n M1, M4,M9 (w/l)=480n/130n M5, M8, M10 (w/l)=1.44u/130n RBIAS 50K C 1pf VDD 500mv Power dissipation 50nw 3dB cutoff frequency 113.4KHZ Pass-band gain 0dB PATMOS2010 18

4. CADENCE Simulation results 4. CADENCE Simulation results 4.1 Transient and AC response o 4.1 Transient and AC response of integrator f integrator 4.2 Cu 4.2 Cutoff freq ff frequen uency t y tuning usin ng using variable integratin g variable integrating capacitor g capacitor 4.3C 3Cut ut of off f f frequ equency Tu ncy Tuning using variable bias cu ning using variable bias current rrent PATMOS2010 19

4.1 Transient and AC response of integrator 4.1 Transient and AC response of integrator PATMOS2010 20

Input signal = ω i ( ) t I sin( t ) in max = I 20 nA max ω = π 2 f = f 1 KHz PATMOS2010 21