1 When Q 0 is true, the bottom NOR-gate actcs like an Q = 1 when at - - PDF document

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Digitalteknik och Datorarkitektur 5hp

Sekventiella kretsar

28 april 2008

karl.marklund@it.uu.se

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B M 1 C A

The function can be described by a thruth table. 4 Minterms The majority function Tools such as Logisim can calculate the thruth table from a circuit ...and minimize the expression using a Karnaugh map... ...and build the minimized circuit for us! För en kombinatorisk krets gäller att det existerar en entydig kombination av utsignal-tillstånd för varje möjlig kombination av insignaler.

En utsignal från en kombinatorisk krets beror ej av kretsens historia dvs tidigare in-signalvärden - kretsen saknar minne!

Därför kan kombinatoriska logiska kretsars funktion beskrivas med hjälp av sanningstabeller.

ALU

OP

Registers

register a 5 bit register b 5 bit register c 5 bit 32 bit 32 bit 32 bit

Vi har sett att vi kan konstruera en ALU med hjälp av kombinatoriska kretstar.

Är detta en kombinatorisk krets?

32 Registers register a

5 bit

register b

5 bit

register c

5 bit

32 bit

ALU

32 bit 32 bit Om det var en kombinatorisk krets skulle vi få samma utdata för samma indata varje gång… OP … och vad är nu det här? På en och samma adress vill vi kunna lagra olika data vid olika tillfällen. En kombinatorisk krets kan inte ha feedback (återkoppling). Vi behöver krestar med minne.

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Q = 1 when at least one of A and B equals 1 Q´ = 0 when at least one of A and B equals 1

1 1 1 Q 1 1 1 1 1 Q´ B A

Q´ = 1 when both A and B equal 0 Q´ = 0 when at least one of A or B equal 1 A pair of cross-coupled NOR-gates. When Q0 is true, the bottom NOR-gate actcs like an inverter (no matter the value of S) and Q1´ becomes false...

... which becomes the input to the top NOR-gate Q1 = true = Q0 (Q is unchanged)

What happens if we change to true here?

Asserting R will give Q = false...

... which becomes the input to the bottom NOR- gate Q’ = true

What happens if we change back to false again?

... which becomes the input to the upper NOR- gate Q = false

Deasserting R won’t change anything, Q remains false no matter the value of R. When both R and S are deasserted, the cross-coupled NOR-gats remembers the values of Q and Q´

What happens if we change to true here?

Asserting S gives Q´ = false...

... which becomes the input to the top NOR-gate Q = true

What happens if we change S back to false?

Deasserting S won’t change anything... Again, when both R and S are deasserted, the cross- coupled NOR-gats remembers the values of Q and Q´

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? 1 Qn Qn+1 ? 1 1 1 1 1 Q´n Q´n+1 S R

Logisim DEMO

1 Qn Qn+1 1 1 1 1 1 Q´n Q´n+1 S R

What happens if both R and S drops (voltage change is not instanteneous) to zero simultaneously? both zero

Overriding the memory feedback action.

R drops first... ... resulting in Q = 1 S drops first... ... resulting in Q = 0

Restricted 1 Qn Qn+1 1 1 1 1 1 Q´n Q´n+1 S R

If both R and S drops to zero at the same time metastability

An example of sequential logic: The output output depends not only on the present input but also on the history of the input.

Restricted 1 Qn Qn+1 1 1 1 1 1 Q´n Q´n+1 S R

R S Q Q´

A SR Latch (Set and Reset Latch) can store 1-bit of data.

SR Latch

D can only function as Set when C (clock/enable) is true.

D Latch

Setting C to 1 will only reset Q if D is 0 at the same time.

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1 Q´n Q´n+1 1 Qn Qn+1 Set 1 1 Reset 1 No Change X Comment D C 1 Q´n Q´n+1 1 Qn Qn+1 Set 1 1 Reset 1 No Change X Comment D C

C D Q Q´

A D Latch (Data Latch) can store 1-bit of data.

SR Latch Restricted 1 Qn Qn+1 1 1

1

1 1

Q´n Q´n+1

S R

R S Q Q´ C D Q Q´

D Latch / Flip-Flop 1 Q´n Q´n+1 1 Qn Qn+1 Set 1 1 Reset 1 No Change X Comment D C

A latch is a sequential device that watches all of its inputs continuously and changes its

• utputs at any time.

A flip-flop is a sequential device that samples its inputs and changes its outputs only at times determined by a clocking signal. C D Q Q´

D Latch 1 Q´n Q´n+1 1 Qn Qn+1 Set 1 1 Reset 1 No Change X Comment D C

C D Q

When the latch is open (C=1) Q follows D (a transparent latch) The output Q of the master latch follows input D when clock is high (which closes the slave latch). Changing C back to zero… Changing C back to zero… …opens the slave latch taking the Q output of the master latch as D input.

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C D Q

Output Q only changes on falling clock edges (non transparent).

1 Q´n Q´n+1 1 Qn Qn+1 Reset Set 1 No Change X non-falling Comment D C 1 Q´n Q´n+1 1 Qn Qn+1 Reset Set 1 No Change X non-falling Comment D C

C D Q Q´

A D Flip-Flop

The inversion bubble

• n the clock input

indicate a falling-edge triggered flip-flop The triangle indicates an edge-trigged latch – a flip flop.

Logisim DEMO

8 bit D flip-flop register

8 D Flip-Flops used to form a 8 bit register.

C D Q Q´

Clock

A falling edge trigged D flip-flop

0001 00112 …output remains unchanged. Clock goes to high... 0001 00112

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…output equals input. Clock falls back to low.... 0001 00112 …does not affect ouput. Changing input .... 1000 11002

ALU

OP

Registers

register a 3 bit register b 3 bit register c 3 bit 8 bit 8 bit 8 bit

We have now built a complete register file. Funkar bra med multiplexer eftersom vi har relativt få register. MEMORY Content Address 0xFFFFFFFF 0xFFFFFFFE 0x00000000 0x00000001 0x00000002 0x00000003 . . . 0xFFFFFFFC 0xFFFFFFFD Varje cell i minnet kan lagra åtta bitar, dvs en byte. I MIPS består minnet av 232 celler. Varje cell har en unik adress. Fyra bytes bildar ett ord (word) om 32 bitar. Kan vi bygga minnet på samma sätt som register-filen? MEMORY Content Address 0xFFFFFFFF 0xFFFFFFFE 0x00000000 0x00000001 0x00000002 0x00000003 . . . 0xFFFFFFFC 0xFFFFFFFD

32 stycken 232 stycken

Giant Multiplexor

Möjligt, men absolut inte praktiskt att bygga ut till 232 olika data inputs... ...och 32 select input.

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What happens if we change to 1 here? All inputs share the same output line. E = Error Signals are not 1

• r 0.... Signals on

the wire are high

• r low voltage.

We cannot have high and low voltage at the same time. Three State Buffer

A B E

High Z 0 (low) 1 (high) 1 (high) 1 (high) 1 (high) 1 (high) 0 (low) E 0 (low) High Z B 0 (low) 0 (low ) A

When Enabled (E = 1) the three state buffer lets the input signal A through. When not Enabled (E = 0) the three state buffer acts lika a huge resistance, kind of cutting of the wire. Output B can be in three states, 0 (low), 1 (high) and high resistance (Z). A three state buffer acts like a true switch compared to a transistor. A tranistor is never completely off,

• nly the number of electrons used to

form the current can be controlled high or low current A multilexor Can use three state buffers to implement a multiplexor.

A shared data line (bus). A shared

• utput data

bus. A D Flip-Flop Using three state buffer instead of multiplerxors make it possible to share data lines.

4x2 SRAM Memory 4x4 SRAM Memory

Address line, aka word line.

4x8 bit = 32 bit = 1 Word

Using three state buffer instead of multiplerxors make it easy to extend...

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Random?

4x4 SRAM Memory

Static Random Access Memory Random: takes the same time to access any random memory location. Static? En kondensator (Capacitor) är som en läckande hink med vatten. Kondensatorn fylls på med elektroner och laddas därmed upp. Efter en tid "rinner" ellektronerna ut och kondensatorn tappar sin laddning. Hmm, en kondensator borde kunna användas för att lagra en bit.... Synd bara att den tappar sitt minne efter ett tag...

Bit Line Word Line

Capacitor Asserting both the Word Line and the Bit Line charges the capacitor

Bit Line Word Line

Write: assert word line, drive new value on bit line.

Read: assert word line, sense value on bit line (destroys saved value) Reading a bit destroys the bit must refresh the memory cell.

Word Lines Bit Lines Bit Cell Sense Amplifier Address High Low Data word line bit line A latch is used to remember a whole word line.

Since real capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically…

DRAM

…because of this refresh requirement, it is a dynamic random access memory as

• pposed to SRAM and
• ther static memory

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Latch

Normal RAM drives many bits (row)

• ut of array, selects few to output.

Adding latch at row outputs allows us to save an entire row of the RAM Later accesses to the RAM can eliminate the row access time, just need column access time Most common in DRAM, page-mode SRAMs also exist

High density (1 ransistor/bit)

Less dense (4-6 transistors/bit) Slower Faster Unstable - needs refresh Stable - holds value as long as power applied

DRAM SRAM

Less expensive per bit More expensive per bit Registers must be as fast as possible, hence Flip-Flop memory similar to SRAM is used for registers. Since we use quite a few registers, the low bit denisity does not matter that much.