PILOT SYSTEM for pxFED upgrade H. STEININGER ( HEPHY Vienna ) - - PowerPoint PPT Presentation

PILOT SYSTEM for pxFED upgrade

Pixel Upgrade Meeting, Grindelwald

30 August, 2012

• H. STEININGER ( HEPHY Vienna )

Gigabit Ethernet RUDP SLink replacement JTAG connector for progr. and diagnosis TTS connector

(old optical receiver has to be removed )

24 channel optical inputs (digital ) LocalBus connection, fast programming option, TTCrx connection

Test connectors serial link

CONNECTOR overview

Gigabit Ethernet RUDP SLink replacement JTAG connector for progr. and diagnosis TTS connector

(old optical receiver has to be removed )

24 channel optical inputs (digital )

New (more powerful) core voltage regulator for last PCB version

not used for PilotSystem: FPGA Zarlink receiver

new connector system no more “slope”

pilot system assembly:

24 chan. input SLink

for the pilot system we can only use 12 input channels / piggy board due to FIFO-I limitations on the FED

Concept:

• ext. CDR

external clock data recovery with ADN2816

• int. DPF

internal digital phase finding ZARLINK receiver

frame finding NRZI decoder deserializer 5b/4b decoder formatting state machine send to FED

piggy board: FED:

special receiving state machine rest of FED uses standard firmware

• ext. CDR
• int. DPF

We decided to use this scheme for our clock recovery to have more security against system jitter and noise. The external clock recovery IC provides a recovered clock and a data signal with stable phase relationship. For this feature we had to include an I2C interface to control this IC. The internal digital phase finding just has to select if we use the positive or negative edge of our 400MHz system clock to register the incoming serial data stream. STATUS: implemented and tested

For the frame finding we are following Ed’s proposal: This leads in a simple schematic to find the correct

• framing. Other methods like finding invalid 5b

symbols would need more logic elements. frame finding NRZI decoder deserializer 5b/4b decoder All parts of this functional block are running with 400MHz

• r 320 MHz. This is a critical frequency for logic blocks
• utside special transceiver blocks (at least for the FPGA

we are using : ALTERA ArriaGX EP1AGX90 ). To run reliable with 400Mhz we had to use tight location constraining for this part of the design. STATUS: implemented and tested

formatting state machine send to FED The test pattern we are sending from the optical test module has the following format: Each of this nibbles (marker words are excluded) is transferred as a 4bit word to the FED together with a 4bit data type word. This enables the FED receiver state machine to correctly form a data pattern which looks like the data pattern from the analog ROC. At the moment we are sending the ROC# instead of the LastDAC information. STATUS: implemented and tested

STATUS: implementing….

FED:

special receiving state machine At the moment we have a special fifo at the FED side to read out and check the date send from the optical test module via VME. Design should be finished in the week after my vacation and it should be possible to read the data out over the Slink (a two channel solution for the first).

PCBs

We have produced 4 piggy boards, two of them with external CDR circuitry. One board without CDR is at Kansas for Gigabit Ethernet tests, the two with CDR are reserved for the pilot system and one for the Vienna lab.

plan:

provide a 12 channel solution till 10/2012