PILOT SYSTEM for pxFED upgrade H. STEININGER ( HEPHY Vienna ) - PowerPoint PPT Presentation

PILOT SYSTEM for pxFED upgrade H. STEININGER ( HEPHY Vienna ) Pixel Upgrade Meeting, Grindelwald 30 August, 2012

CONNECTOR overview Test connectors serial link Gigabit Ethernet RUDP SLink replacement JTAG connector for progr. and diagnosis TTS connector (old optical receiver has to be removed ) 24 channel optical inputs (digital ) LocalBus connection, fast programming option, TTCrx connection

New (more powerful) core voltage regulator for last PCB version not used for PilotSystem: Gigabit Ethernet RUDP SLink replacement JTAG connector for progr. and diagnosis TTS connector (old optical receiver has to be removed ) 24 channel optical inputs (digital ) FPGA new connector system Zarlink receiver no more “slope”

pilot system assembly: for the pilot system we can only use SLink 12 input channels / piggy board 24 chan. input due to FIFO-I limitations on the FED

Concept: piggy board: frame finding formatting state NRZI machine decoder ZARLINK ext. CDR int. DPF send to receiver deserializer FED external clock internal digital data recovery phase finding 5b/4b with ADN2816 decoder FED: rest of special FED receiving state uses standard firmware machine

ext. CDR int. DPF We decided to use this scheme for our clock recovery to have more security against system jitter and noise. The external clock recovery IC provides a recovered clock and a data signal with stable phase relationship. For this feature we had to include an I2C interface to control this IC. The internal digital phase finding just has to select if we use the positive or negative edge of our 400MHz system clock to register the incoming serial data stream. STATUS: implemented and tested

For the frame finding we are following Ed’s frame proposal: finding NRZI decoder deserializer 5b/4b This leads in a simple schematic to find the correct decoder framing. Other methods like finding invalid 5b symbols would need more logic elements. All parts of this functional block are running with 400MHz or 320 MHz. This is a critical frequency for logic blocks outside special transceiver blocks (at least for the FPGA we are using : ALTERA ArriaGX EP1AGX90 ). To run reliable with 400Mhz we had to use tight location constraining for this part of the design. STATUS: implemented and tested

The test pattern we are sending from the optical formatting test module has the following format: state machine send to FED Each of this nibbles (marker words are excluded) is transferred as a 4bit word to the FED together with a 4bit data type word. This enables the FED receiver state machine to correctly form a data pattern which looks like the data pattern from the analog ROC. At the moment we are sending the ROC# instead of the LastDAC information. STATUS: implemented and tested

FED: special receiving state machine At the moment we have a special fifo at the FED side to read out and check the date send from the optical test module via VME. Design should be finished in the week after my vacation and it should be possible to read the data out over the Slink (a two channel solution for the first). STATUS: implementing….

PCBs We have produced 4 piggy boards, two of them with external CDR circuitry. One board without CDR is at Kansas for Gigabit Ethernet tests, the two with CDR are reserved for the pilot system and one for the Vienna lab. plan: provide a 12 channel solution till 10/2012