Sequential circuits Analysis March 13, 2020 Patrice Belleville / Geoffrey Tien 1
Announcements • Midterm 2: Tuesday, March 17, 17:00 – 18:15 (75 minutes) – Last names A to K: WOOD 2 – Last names L to S: CIRS 1250 – Last names T to Z: ESB 1013 • Coverage: Modules 5 to 9 (up to the end of Friday’s class) + Labs 4 to 7 – Predicate logic, sets, inferences with predicate logic, proof techniques, sequential circuits • See Piazza for details, course webpage for past quizzes and midterms March 13, 2020 Patrice Belleville / Geoffrey Tien 2
Latches vs flip-flops Trigger warning! • Latches are level-triggered – state can change any time the control/enable is at a particular level (high or low) • Flip-flops are edge-triggered – state can change only when the control input changes level (low to high or high to low) 𝑅 1 𝑅 2 C D 𝑅 1 𝑅 2 Time March 13, 2020 Patrice Belleville / Geoffrey Tien 3
Level trigger vs. edge trigger • More complex sequential systems often involve multiple "memory" bits that must all operate and change at the same time – each memory bit may be affected by logic pathways of different lengths and hence different amounts of gate delay • Connecting multiple edge-triggered sequential devices to a common control signal allows different pathways to stabilize in varying amounts of time – once all sequential inputs are known to have stabilized (fully propagated through combinational components), the control signal activates all connected sequential devices at once, and inputs are processed only at the moment of activation March 13, 2020 Patrice Belleville / Geoffrey Tien 4
Sequential circuit analysis Worksheet • Consider the following circuit. What is its behaviour on each clock cycle? March 13, 2020 Patrice Belleville / Geoffrey Tien 5
Sequential circuit analysis Input equations • Sequential circuits consist of latches/flip-flops and combinational components – combination circuits may produce outputs that are connected to the input signals of flip-flops • the Boolean functions for these are called flip-flop input equations – The variable for the Boolean function's output is usually denoted by the flip-flop input label with a numbered subscript – This function fully specifies the combinational logic which drives the flip-flop's behaviour in the overall sequential system – e.g. Input equations: 𝑒 1 = 𝑦 ∧ ~𝑅 1 𝑒 0 = 𝑅 1 ∨ ~𝑅 0 March 13, 2020 Patrice Belleville / Geoffrey Tien 6
Sequential circuit analysis Example – input equations + + + + 𝑅 1 𝑅 0 𝑦 𝑧 𝑒 1 𝑒 0 𝑅 1 𝑅 0 𝑅 1 𝑅 0 𝑦 𝑅 1 𝑅 0 functional description: 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 x Q1 0 1 1 0 1 1 Q0 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 March 13, 2020 Patrice Belleville / Geoffrey Tien 7
Exercise Sequential circuit analysis • Determine the behaviour of the following sequential system: March 13, 2020 Patrice Belleville / Geoffrey Tien 8
Sequential circuits Design March 13, 2020 Patrice Belleville / Geoffrey Tien 9
Sequential circuit design • All of the same techniques of design and analysis from combinational circuits also apply to sequential design – Karnaugh maps, recognizers, etc. – Now, the system state (flip-flop outputs) are included as "inputs" • We start with a specification of the states, transitions, inputs, and sequential devices to be used in the construction – based on the understood behaviour of the sequential device (e.g. D flip- flop or register), and the required transition, determine the inputs necessary to cause the required transition to occur March 13, 2020 Patrice Belleville / Geoffrey Tien 10
Sequential circuit design • Example: design a sequential system with two bits of state and two external inputs, 𝑣𝑞 and 𝑒𝑜 , with the following behaviour: – do nothing when 𝑣𝑞 = 0 and 𝑒𝑜 = 0 – Reset state to 0 when 𝑣𝑞 = 1 and 𝑒𝑜 = 1 – increment the state when 𝑣𝑞 = 1 and 𝑒𝑜 = 0 – decrement the state when 𝑣𝑞 = 0 and 𝑒𝑜 = 1 • An up/down counter with reset March 13, 2020 Patrice Belleville / Geoffrey Tien 11
Sequential circuit design Up/down counter with reset • Approach 1: individual bits of state implemented using D flip- flops – Construct a truth table • current state and external inputs as "input" • next state as "output" • determine propositional logic statements/functions to produce the necessary transition from each current state to the next state. March 13, 2020 Patrice Belleville / Geoffrey Tien 12
Sequential circuit design Up/down counter with reset – approach 1 + + 𝑹 𝟐 𝑹 𝟏 𝒗𝒒 𝒆𝒐 𝑹 𝟐 𝑹 𝟏 𝒆 𝟐 𝒆 𝟏 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 The 𝑒 columns will be the 1 0 0 1 same as the 𝑅 + columns 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 March 13, 2020 Patrice Belleville / Geoffrey Tien 13
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