Viterbi Algorithm Saravanan Vijayakumaran sarva@ee.iitb.ac.in - - PowerPoint PPT Presentation

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Viterbi Algorithm Saravanan Vijayakumaran sarva@ee.iitb.ac.in - - PowerPoint PPT Presentation

Viterbi Algorithm Saravanan Vijayakumaran sarva@ee.iitb.ac.in Department of Electrical Engineering Indian Institute of Technology Bombay October 30, 2014 1 / 9 Encoder State Diagram 1 + D 2 1 + D + D 2 G ( D ) = 1 + D 0/000 v ( 0 )


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SLIDE 1

Viterbi Algorithm

Saravanan Vijayakumaran sarva@ee.iitb.ac.in

Department of Electrical Engineering Indian Institute of Technology Bombay

October 30, 2014

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SLIDE 2

Encoder State Diagram

G(D) =

  • 1 + D

1 + D2 1 + D + D2

+ + + u v(0) v(1) v(2)

S0 S1 S3 S2 1/111 0/000 1/010 0/101 0/110 1/001 1/100 0/011

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SLIDE 3

Encoder Trellis Diagram

S0 S0 S0 S0 S0 S0 S0 S2 S2 S2 S2 S2 S1 S1 S1 S1 S1 S1 S3 S3 S3 S3 S3

· · · · · · · · · · · ·

000 000 000 000 000 000 001 001 001 001 111 111 111 111 111 111 011 011 011 011 010 010 010 010 010 101 101 101 101 101 100 100 100 100 110 110 110 110

  • The initial state of the encoder is the all-zeros state
  • Every path in the trellis starting from the initial state corresponds to a

codeword

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SLIDE 4

Terminated Trellis Diagram

S0 S0 S0 S0 S0 S0 S0 S0 S2 S2 S2 S2 S2 S1 S1 S1 S1 S1 S3 S3 S3 S3 000 000 000 000 000 000 000 001 001 001 111 111 111 111 111 011 011 011 011 011 010 010 010 010 101 101 101 101 101 100 100 100 110 110 110 110

  • The inputs are chosen to terminate the trellis in the all-zeros state
  • Every path from the initial state to the final state is a codeword

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SLIDE 5

Terminating the Trellis of Feedforward Encoders

+ + + u v(0) v(1) v(2)

  • Two consecutive zero input bits will drive the above

encoder to the all-zeros state

  • In a feedforward encoder with memory order m, m

consecutive zero input bits in each of the k inputs will terminate the trellis

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SLIDE 6

Terminating the Trellis of Feedback Encoders

wi−1 wi−2 wi−m + + + + + + + + f0 f1 f2 fm−1 fm q1 q2 qm−1 qm

· · · · · · · · ·

ui wi vi

  • To reach the all-zeros state, the input to the shift register

has to be zero for m time units wi = 0 = ⇒ ui =

m

  • j=1

qjwi−j

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SLIDE 7

Maximum Likelihood Decoder for BSC

S0 S0 S0 S0 S0 S0 S0 S0 S2 S2 S2 S2 S2 S1 S1 S1 S1 S1 S3 S3 S3 S3 000 000 000 000 000 000 000 001 001 001 111 111 111 111 111 011 011 011 011 011 010 010 010 010 101 101 101 101 101 100 100 100 110 110 110 110

  • Let r =
  • 110

110 110 111 010 101 101

  • be the BSC output
  • The ML decoder will output a codeword v such that dH(r, v) is minimum
  • The Viterbi algorithm is an efficient way to find the v closest to r

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SLIDE 8

Maximum Likelihood Decoder for BSC

S0 S0 S0 S0 S0 S0 S0 S0 S2 S2 S2 S2 S2 S1 S1 S1 S1 S1 S3 S3 S3 S3 2 2 2 3 1 2 2 3 2 2 1 1 1 2 2 1 1 2 2 1 1 2 2 2 1 3 3 2 2 3 2 2 2

  • Branch metric is the Hamming distance between the codeword bits of a

state transition and the corresponding received bits

  • Path metric is the sum of all the branch metrics along a path

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SLIDE 9

Questions? Takeaways?

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