Viterbi Algorithm
Saravanan Vijayakumaran sarva@ee.iitb.ac.in
Department of Electrical Engineering Indian Institute of Technology Bombay
October 30, 2014
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Viterbi Algorithm Saravanan Vijayakumaran sarva@ee.iitb.ac.in - - PowerPoint PPT Presentation
Viterbi Algorithm Saravanan Vijayakumaran sarva@ee.iitb.ac.in Department of Electrical Engineering Indian Institute of Technology Bombay October 30, 2014 1 / 9 Encoder State Diagram 1 + D 2 1 + D + D 2 G ( D ) = 1 + D 0/000 v ( 0 )
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+ + + u v(0) v(1) v(2)
S0 S1 S3 S2 1/111 0/000 1/010 0/101 0/110 1/001 1/100 0/011
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S0 S0 S0 S0 S0 S0 S0 S2 S2 S2 S2 S2 S1 S1 S1 S1 S1 S1 S3 S3 S3 S3 S3
000 000 000 000 000 000 001 001 001 001 111 111 111 111 111 111 011 011 011 011 010 010 010 010 010 101 101 101 101 101 100 100 100 100 110 110 110 110
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S0 S0 S0 S0 S0 S0 S0 S0 S2 S2 S2 S2 S2 S1 S1 S1 S1 S1 S3 S3 S3 S3 000 000 000 000 000 000 000 001 001 001 111 111 111 111 111 011 011 011 011 011 010 010 010 010 101 101 101 101 101 100 100 100 110 110 110 110
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· · · · · · · · ·
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S0 S0 S0 S0 S0 S0 S0 S0 S2 S2 S2 S2 S2 S1 S1 S1 S1 S1 S3 S3 S3 S3 000 000 000 000 000 000 000 001 001 001 111 111 111 111 111 011 011 011 011 011 010 010 010 010 101 101 101 101 101 100 100 100 110 110 110 110
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S0 S0 S0 S0 S0 S0 S0 S0 S2 S2 S2 S2 S2 S1 S1 S1 S1 S1 S3 S3 S3 S3 2 2 2 3 1 2 2 3 2 2 1 1 1 2 2 1 1 2 2 1 1 2 2 2 1 3 3 2 2 3 2 2 2
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