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VIRTUES AND LIMITATIONS OF COMMODITY HARDWARE TRANSACTIONAL MEMORY - - PowerPoint PPT Presentation

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PACT 2014 VIRTUES AND LIMITATIONS OF COMMODITY HARDWARE TRANSACTIONAL MEMORY Nuno Diegues, Paolo Romano and Lus Rodrigues 2 Virtues and Limitations of HTM PACT 2014 The multi-core (r)evolution 2 Virtues and Limitations of HTM PACT 2014

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VIRTUES AND LIMITATIONS OF COMMODITY HARDWARE TRANSACTIONAL MEMORY

Nuno Diegues, Paolo Romano and Luís Rodrigues

PACT 2014

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The multi-core (r)evolution

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Multi-cores are now ubiquitous

The multi-core (r)evolution

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Multi-cores are now ubiquitous

The multi-core (r)evolution

Shared Memory

CPU1 CPU2 CPU3 CPU4

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Virtues and Limitations of HTM PACT 2014

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Multi-cores are now ubiquitous

The multi-core (r)evolution

Shared Memory

CPU1 CPU2 CPU3 CPU4

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Virtues and Limitations of HTM PACT 2014

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Multi-cores are now ubiquitous

The multi-core (r)evolution

Shared Memory

CPU1 CPU2 CPU3 CPU4

Concurrent programming is complex

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Virtues and Limitations of HTM PACT 2014

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Multi-cores are now ubiquitous

The multi-core (r)evolution

Shared Memory

CPU1 CPU2 CPU3 CPU4

Concurrent programming is complex

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Virtues and Limitations of HTM PACT 2014

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Multi-cores are now ubiquitous

The multi-core (r)evolution

Shared Memory

CPU1 CPU2 CPU3 CPU4

Concurrent programming is complex

Hard to get right:

  • fine-grained locks
  • deadlocks
  • correctness

Classic approach: Locking

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Virtues and Limitations of HTM PACT 2014

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Multi-cores are now ubiquitous

The multi-core (r)evolution

Shared Memory

CPU1 CPU2 CPU3 CPU4

Concurrent programming is complex

Hard to get right:

  • fine-grained locks
  • deadlocks
  • correctness

Classic approach: Locking

atomic { withdraw(acc1,val); deposit(acc2,val); }

Transactional Memory abstraction Programmer identifies atomic blocks Runtime implements synchronization

Transactional Memory System

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TM is now available in commodity processors

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TM is now available in commodity processors

  • Intel: Haswell in desktops, laptops, tablets, servers…
  • IBM: BG/Q, zEC12, Power8
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Virtues and Limitations of HTM PACT 2014

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TM is now available in commodity processors

Over 10 years of:

  • Software implementations (STMs)
  • Simulations of HTMs and HybridTMs
  • Intel: Haswell in desktops, laptops, tablets, servers…
  • IBM: BG/Q, zEC12, Power8
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Virtues and Limitations of HTM PACT 2014

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TM is now available in commodity processors

Over 10 years of:

  • Software implementations (STMs)
  • Simulations of HTMs and HybridTMs
  • Intel: Haswell in desktops, laptops, tablets, servers…
  • IBM: BG/Q, zEC12, Power8

Where does commodity HTM stand in the big picture?

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Virtues and Limitations of HTM PACT 2014

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TM is now available in commodity processors

Over 10 years of:

  • Software implementations (STMs)
  • Simulations of HTMs and HybridTMs
  • Intel: Haswell in desktops, laptops, tablets, servers…
  • IBM: BG/Q, zEC12, Power8

Where does commodity HTM stand in the big picture? Our contribution: largest TM study to date

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Virtues and Limitations of HTM PACT 2014

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TM is now available in commodity processors

Over 10 years of:

  • Software implementations (STMs)
  • Simulations of HTMs and HybridTMs
  • Intel: Haswell in desktops, laptops, tablets, servers…
  • IBM: BG/Q, zEC12, Power8

Where does commodity HTM stand in the big picture? Our contribution: largest TM study to date

Framework with 4 STMs, Intel HTM, 2 HyTMs and locking strategies; Metrics for performance and power consumption; 10 benchmarks.

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HTM: Intel Transactional Synchronization Extensions (TSX)

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HTM: Intel Transactional Synchronization Extensions (TSX)

Widely available in millions of machines Similar in nature to IBM’s HTMs

CPU1 CPU2

Memory Bus

L1 Cache L1 Cache L2 Cache L2 Cache 64KB 256KB L3 Cache

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HTM: Intel Transactional Synchronization Extensions (TSX)

Widely available in millions of machines Similar in nature to IBM’s HTMs

CPU1 CPU2

Memory Bus

L1 Cache L1 Cache L2 Cache L2 Cache 64KB 256KB L3 Cache

  • L1 modified to be transactional
  • Cache coherence detects conflicts eagerly
  • Strong atomicity
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HTM: Intel Transactional Synchronization Extensions (TSX)

CPU1 CPU2

Memory Bus

L1 Cache L1 Cache L2 Cache L2 Cache L3 Cache

CPU 1 CPU 2

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HTM: Intel Transactional Synchronization Extensions (TSX)

CPU1 CPU2

Memory Bus

L1 Cache L1 Cache L2 Cache L2 Cache L3 Cache

CPU 1 CPU 2 xbegin

TSX: on

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HTM: Intel Transactional Synchronization Extensions (TSX)

CPU1 CPU2

Memory Bus

L1 Cache L1 Cache L2 Cache L2 Cache L3 Cache

CPU 1 CPU 2 xbegin

TSX: on

read x: 0 // Set bit read on x cache line

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HTM: Intel Transactional Synchronization Extensions (TSX)

CPU1 CPU2

Memory Bus

L1 Cache L1 Cache L2 Cache L2 Cache L3 Cache

CPU 1 CPU 2 xbegin

TSX: on

read x: 0 // Set bit read on x cache line

x: 0 -- r

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HTM: Intel Transactional Synchronization Extensions (TSX)

CPU1 CPU2

Memory Bus

L1 Cache L1 Cache L2 Cache L2 Cache L3 Cache

CPU 1 CPU 2 xbegin

TSX: on

read x: 0 // Set bit read on x cache line

x: 0 -- r

write y = 1 // Buffer write in L1 cache

y: 1 -- w

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HTM: Intel Transactional Synchronization Extensions (TSX)

CPU1 CPU2

Memory Bus

L1 Cache L1 Cache L2 Cache L2 Cache L3 Cache

CPU 1 CPU 2 xbegin read x: 0 // Set bit read on x cache line write y = 1 // Buffer write in L1 cache xend // Atomically clean bits and publish

x: 0 y: 1

…

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HTM: Intel Transactional Synchronization Extensions (TSX)

CPU1 CPU2

Memory Bus

L1 Cache L1 Cache L2 Cache L2 Cache L3 Cache

CPU 1 CPU 2 xbegin read x: 0 // Set bit read on x cache line write y = 1 // Buffer write in L1 cache xend // Atomically clean bits and publish

x: 0 y: 1

xbegin read y: 1

…

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HTM: Intel Transactional Synchronization Extensions (TSX)

CPU1 CPU2

Memory Bus

L1 Cache L1 Cache L2 Cache L2 Cache L3 Cache

CPU 1 CPU 2 xbegin read x: 0 // Set bit read on x cache line write y = 1 // Buffer write in L1 cache xend // Atomically clean bits and publish

x: 0 y: 1

xbegin read y: 1

…

y: 1 -- r

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HTM: Intel Transactional Synchronization Extensions (TSX)

CPU1 CPU2

Memory Bus

L1 Cache L1 Cache L2 Cache L2 Cache L3 Cache

CPU 1 CPU 2 xbegin read x: 0 // Set bit read on x cache line write y = 1 // Buffer write in L1 cache xend // Atomically clean bits and publish

x: 0 y: 1

xbegin read y: 1 write y = 2

… …

y: 1 -- r

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HTM: Intel Transactional Synchronization Extensions (TSX)

CPU1 CPU2

Memory Bus

L1 Cache L1 Cache L2 Cache L2 Cache L3 Cache

CPU 1 CPU 2 xbegin read x: 0 // Set bit read on x cache line write y = 1 // Buffer write in L1 cache xend // Atomically clean bits and publish xbegin read y: 1 write y = 2

… …

y: 1 -- r x: 0 y: 2

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HTM: Intel Transactional Synchronization Extensions (TSX)

CPU1 CPU2

Memory Bus

L1 Cache L1 Cache L2 Cache L2 Cache L3 Cache

CPU 1 CPU 2 xbegin read x: 0 // Set bit read on x cache line write y = 1 // Buffer write in L1 cache xend // Atomically clean bits and publish xbegin read y: 1 write y = 2 xabort invalidation

snooped write invalidates tx read

… …

y: 1 -- r x: 0 y: 2

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In an ideal world…

xbegin widthdraw(acc1,val) deposit(acc2,val) xend

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In an ideal world…

xbegin widthdraw(acc1,val) deposit(acc2,val) xend

Transactions may abort:

  • because of contention on same

memory locations

Transactions restart

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In an ideal world…

xbegin widthdraw(acc1,val) deposit(acc2,val) xend

Transactions may abort:

  • because of contention on same

memory locations

…and every transaction shall eventually succeed

Transactions restart

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…in practice: Best-Effort Nature

No progress guarantees:

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…in practice: Best-Effort Nature

No progress guarantees:

  • A transaction may always abort

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…in practice: Best-Effort Nature

No progress guarantees:

  • A transaction may always abort


…due to a number of reasons:

  • Forbidden instructions
  • Capacity of caches
  • Faults and signals
  • Contending transactions, aborting each other
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Restrictions of TSX

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  • Writes:
  • size of L1 cache: 32KB
  • non-negligible aborts for >8KB
  • cache associativity

Restrictions of TSX

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  • Writes:
  • size of L1 cache: 32KB
  • non-negligible aborts for >8KB
  • cache associativity

Restrictions of TSX

  • Reads:
  • up to 4MB
  • overflow structure in L2 cache
  • presumed to be a Bloom-Filter [Eurosys14]
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  • Writes:
  • size of L1 cache: 32KB
  • non-negligible aborts for >8KB
  • cache associativity

Restrictions of TSX

  • Reads:
  • up to 4MB
  • overflow structure in L2 cache
  • presumed to be a Bloom-Filter [Eurosys14]
  • Interrupts:
  • up to 1M cycles
  • Roughly 0.5 ms on a Haswell Xeon
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  • Writes:
  • size of L1 cache: 32KB
  • non-negligible aborts for >8KB
  • cache associativity

Restrictions of TSX

  • Reads:
  • up to 4MB
  • overflow structure in L2 cache
  • presumed to be a Bloom-Filter [Eurosys14]
  • Interrupts:
  • up to 1M cycles
  • Roughly 0.5 ms on a Haswell Xeon

TSX alone is not enough

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TSX with a fall-back

start: int status = xbegin if (status == ok) // != ok when aborted if (fallback-in-use()) xabort // fall-back in use else goto code // fast-path

!

if (shouldRetry()) // retry policy goto start else use-fallback() // use fall-back

!

code: application logic

!

if (inFastPath) xend // fast-path else quit-fallback() // fall-back

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TSX with a fall-back: a single lock

start: int status = xbegin if (status == ok) // != ok when aborted if (isTaken(lock)) xabort // fall-back in use else goto code // fast-path

!

if (shouldRetry()) // retry policy goto start else acquire(lock) // use fall-back

!

code: application logic

!

if (inFastPath) // fast-path xend else // fall-back release(lock)

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Lesson #1

Tuning best-effort HTMs is extremely important

The hardware is only a part of the solution.

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Lesson #1

Tuning best-effort HTMs is extremely important

The hardware is only a part of the solution. Avoid HLE when possible

  • the fallback is triggered too often
  • cannot be tuned
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Lesson #1

Tuning best-effort HTMs is extremely important

The hardware is only a part of the solution. 2x improvement by choosing the best configuration on average across all workloads. Avoid HLE when possible

  • the fallback is triggered too often
  • cannot be tuned
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Lesson #1: Tuning TSX

Which fall-back to use?

  • Lock implementation

!

When to take the fall-back?

  • Retry policy
  • Contention management
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Lesson #1: Tuning TSX

Which fall-back to use?

  • Lock implementation

!

When to take the fall-back?

  • Retry policy
  • Contention management

Overhead (%) Lock Performance Power Ticket 1.0 1.1 MCS 2.4 1.2 CLH 2.9 2.4 RW 14.2 17.4 TTAS 15.2 17.4 Spin 16.4 17.5 average across all benchmarks and thread counts

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Lesson #1: Tuning TSX

Which fall-back to use?

  • Lock implementation

!

When to take the fall-back?

  • Retry policy
  • Contention management

Overhead (%) Lock Performance Power Ticket 1.0 1.1 MCS 2.4 1.2 CLH 2.9 2.4 RW 14.2 17.4 TTAS 15.2 17.4 Spin 16.4 17.5 average across all benchmarks and thread counts Avoid lemming effect [ASPLOS12]

  • avalanche aborts that exhaust retry policy

!

Manage contention with auxiliary lock [PPOPP13]

  • fallback lock creates spurious aborts

!

Retry policy using literature values [HPC13,HPCA14]

  • give up on HTM after a threshold of aborts
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Software TM in the picture

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Software TM in the picture

int i = 0!

!

…!

!

atomic {! i++! } Source program

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Software TM in the picture

int i = 0!

!

…!

!

atomic {! i++! } int i = 0! …! TM.begin-tx()! int tmp = TM.read(&i)! tmp++! TM.write(&i, tmp)! TM.end-tx() Source program Compiled program instrumentation

!

to invoke STM

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Software TM in the picture

int i = 0!

!

…!

!

atomic {! i++! } int i = 0! …! TM.begin-tx()! int tmp = TM.read(&i)! tmp++! TM.write(&i, tmp)! TM.end-tx() Source program Compiled program instrumentation

!

to invoke STM Over 10 years of research on STM ➔ many prototypes and designs. We considered four state of the art implementations:

  • TL2: commit-time locking, used in Intel paper for comparison with TSX
  • Norec: single commit lock, least instrumentation overhead
  • TinySTM: encounter-time locking
  • SwissTM: lazy val for r/w and eager for w/w; novel contention manager
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Fall-backs for best-effort HTM

Single global lock

  • as seen before
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Fall-backs for best-effort HTM

Single global lock

  • as seen before

Fine-grained locks

  • possibly check more than one lock
  • requires programmer to define which and how many locks
  • r automatic lock inference techniques [Transact06,LCPC13]
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Fall-backs for best-effort HTM

Single global lock

  • as seen before

STMs

  • separate code paths
  • uninstrumented for fast path in HTM
  • instrumented reads and writes for STM
  • use HTM to boost STM commit [SPAA13]
  • NOrec and TL2 for HybridTMs

Fine-grained locks

  • possibly check more than one lock
  • requires programmer to define which and how many locks
  • r automatic lock inference techniques [Transact06,LCPC13]
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Fall-backs for best-effort HTM

Single global lock

  • as seen before
  • tomorrow: Invyswell

STMs

  • separate code paths
  • uninstrumented for fast path in HTM
  • instrumented reads and writes for STM
  • use HTM to boost STM commit [SPAA13]
  • NOrec and TL2 for HybridTMs

Fine-grained locks

  • possibly check more than one lock
  • requires programmer to define which and how many locks
  • r automatic lock inference techniques [Transact06,LCPC13]
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Experimental settings

GL FL

!

TSX-GL TSX-FL

!

TL2 NOrec SwissTM TinySTM

!

TSX-TL2 TSX-NOrec Locking HTM STM HyTM

Synchronization techniques under comparison:

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Target machine:

  • Intel Haswell Xeon E3-1275v3 3.5GHz (3.9GHz Turbo)
  • 4 cores, 8 hardware threads (via hyper-threading)

! !

Standard metrics for evaluation:

  • Time to complete benchmarks
  • presented as speedup
  • Energy consumed (collected via Intel RAPL)
  • presented as relative energy
  • The baseline for comparison is a sequential, non-synchronized execution

! !

Benchmarks:

  • 7 STAMP benchmarks
  • Memcached [ASPLOS14]
  • Concurrent data-structures

Experimental settings

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Lesson #2: HTM is not a silver bullet

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Lesson #2: HTM is not a silver bullet

Tested 900 scenarios (STAMP+data structures)

Identified three categories of applications:

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Lesson #2: HTM is not a silver bullet

  • 1. Uncontested winner
  • concurrent data structures
  • STAMP: small, occasional transactions

Tested 900 scenarios (STAMP+data structures)

Identified three categories of applications:

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Lesson #2: HTM is not a silver bullet

  • 1. Uncontested winner
  • concurrent data structures
  • STAMP: small, occasional transactions

Tested 900 scenarios (STAMP+data structures)

Identified three categories of applications:

Kmeans

TSX-GL TSX-NOrec TinySTM

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Lesson #2: HTM is not a silver bullet

  • 1. Uncontested winner
  • concurrent data structures
  • STAMP: small, occasional transactions

Tested 900 scenarios (STAMP+data structures)

Identified three categories of applications:

  • 2. Only better without hyper-threading
  • more competitive energy-wise
  • spurious aborts due to hw restrictions

TSX-GL TSX-NOrec TinySTM

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Lesson #2: HTM is not a silver bullet

  • 1. Uncontested winner
  • concurrent data structures
  • STAMP: small, occasional transactions

Tested 900 scenarios (STAMP+data structures)

Identified three categories of applications:

  • 2. Only better without hyper-threading
  • more competitive energy-wise
  • spurious aborts due to hw restrictions

Intruder

TSX-GL TSX-NOrec TinySTM

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Lesson #2: HTM is not a silver bullet

  • 1. Uncontested winner
  • concurrent data structures
  • STAMP: small, occasional transactions

Tested 900 scenarios (STAMP+data structures)

Identified three categories of applications:

  • 2. Only better without hyper-threading
  • more competitive energy-wise
  • spurious aborts due to hw restrictions
  • 3. Always worse than others
  • except for single-threaded execution
  • capacity aborts and quantum exhaustion

TSX-GL TSX-NOrec TinySTM

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Lesson #2: HTM is not a silver bullet

  • 1. Uncontested winner
  • concurrent data structures
  • STAMP: small, occasional transactions

Tested 900 scenarios (STAMP+data structures)

Identified three categories of applications:

  • 2. Only better without hyper-threading
  • more competitive energy-wise
  • spurious aborts due to hw restrictions
  • 3. Always worse than others
  • except for single-threaded execution
  • capacity aborts and quantum exhaustion

Yada

TSX-GL TSX-NOrec TinySTM

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Lesson #3: STM is still very competitive

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Most robust all-around solution

  • albeit more power hungry than HTM-based approaches

Lesson #3: STM is still very competitive

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Most robust all-around solution

  • albeit more power hungry than HTM-based approaches

Lesson #3: STM is still very competitive

Considering the best STM (SwissTM would be similar)

Relative time Relative energy

TSX-GL TSX-NOrec TinySTM

All STAMP benchmarks

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Most robust all-around solution

  • albeit more power hungry than HTM-based approaches

Lesson #3: STM is still very competitive

Considering the best STM (SwissTM would be similar)

Relative time Relative energy

  • Worst at 1 thread

TSX-GL TSX-NOrec TinySTM

All STAMP benchmarks

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Most robust all-around solution

  • albeit more power hungry than HTM-based approaches

Lesson #3: STM is still very competitive

Considering the best STM (SwissTM would be similar)

Relative time Relative energy

  • Worst at 1 thread
  • Turning point at 3 threads

TSX-GL TSX-NOrec TinySTM

All STAMP benchmarks

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Most robust all-around solution

  • albeit more power hungry than HTM-based approaches

Lesson #3: STM is still very competitive

Considering the best STM (SwissTM would be similar)

Relative time Relative energy

  • Worst at 1 thread
  • Turning point at 3 threads
  • 84% more performance, 46% more energy-efficiency (over TSX-GL)

TSX-GL TSX-NOrec TinySTM

All STAMP benchmarks

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Lesson #4: Fine-grained locking is not worth it

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Lesson #4: Fine-grained locking is not worth it

Speedup Relative Energy

Sub-set of benchmarks with fine-grained locks

HTM is able to achieve the same degree of parallelism

  • TSX-FL checks more locks in each transaction on average
  • tends to be worse than TSX-GL

TSX-GL FL TSX-FL TinySTM

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Lesson #4: Fine-grained locking is not worth it

Speedup Relative Energy

Sub-set of benchmarks with fine-grained locks

HTM is able to achieve the same degree of parallelism

  • TSX-FL checks more locks in each transaction on average
  • tends to be worse than TSX-GL

Benchmarks include concurrent data-structures

  • small transactions benefit HTM or FL approaches

TSX-GL FL TSX-FL TinySTM

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Research Directions: HybridTMs

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Research Directions: HybridTMs

None of the evaluated HybridTMs is ever the best approach

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Research Directions: HybridTMs

TSX-GL TSX-NOrec TinySTM

All STAMP benchmarks None of the evaluated HybridTMs is ever the best approach

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Research Directions: HybridTMs

TSX-GL TSX-NOrec TinySTM

All STAMP benchmarks None of the evaluated HybridTMs is ever the best approach

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Research Directions: HybridTMs

TSX-GL TSX-NOrec TinySTM

!

  • Spurious aborts from fallback of STM with HTM
  • More efficient algorithms exist with non-transactional operations
  • Not available on Intel TSX or IBM BG/Q
  • Is it a requirement for efficient future HybridTMs?

All STAMP benchmarks None of the evaluated HybridTMs is ever the best approach

Speedup Relative Energy

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Research Directions: Compiler Instrumentation

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Research Directions: Compiler Instrumentation

STMs (and HybridTM’s software path) used manual instrumentation.

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Research Directions: Compiler Instrumentation

STMs (and HybridTM’s software path) used manual instrumentation. What changes if we rely on the compiler?

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Research Directions: Compiler Instrumentation

STMs (and HybridTM’s software path) used manual instrumentation. What changes if we rely on the compiler? GCC 4.8

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Research Directions: Compiler Instrumentation

STMs (and HybridTM’s software path) used manual instrumentation. What changes if we rely on the compiler?

  • Read- and write-sets can increase up to 3x (in SSCA2)
  • Conservative compiler instruments accesses that are clearly not shared
  • Even simple static analysis (such as those in Clang) would improve

GCC 4.8

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Also important for HTM:

  • If non-transactional operations are available
  • May reduce capacity aborts

Research Directions: Compiler Instrumentation

STMs (and HybridTM’s software path) used manual instrumentation. What changes if we rely on the compiler?

  • Read- and write-sets can increase up to 3x (in SSCA2)
  • Conservative compiler instruments accesses that are clearly not shared
  • Even simple static analysis (such as those in Clang) would improve

GCC 4.8

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Research Directions: Automatic HTM tuning

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Research Directions: Automatic HTM tuning

We used the best tuning of TSX on average.

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Research Directions: Automatic HTM tuning

We used the best tuning of TSX on average. But what about the optimal for each case?

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Research Directions: Automatic HTM tuning

We used the best tuning of TSX on average. But what about the optimal for each case?

Speedup % Kmeans SSCA2 Intruder Vacation Genome Yada Labyrinth

4 threads 12 7 20 36 12 13 2 8 threads 5 8 80 21 2 55 39 Time improvement of optimal vs average

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Research Directions: Automatic HTM tuning

Technique for optimal tuning, focus only on performance:

  • Self-Tuning Intel TSX --- Best paper at USENIX ICAC’14

We used the best tuning of TSX on average. But what about the optimal for each case?

Speedup % Kmeans SSCA2 Intruder Vacation Genome Yada Labyrinth

4 threads 12 7 20 36 12 13 2 8 threads 5 8 80 21 2 55 39 Time improvement of optimal vs average

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Summary

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Summary

HTM is not a silver bullet

  • Shines with short infrequent transactions and concurrent data structures
  • Great in energy efficiency and at low thread count
  • Hyper-threading amplifies HTM’s inherent limitations
  • HTM requires careful tuning of parameters governing the fallback:
  • automatic tuning is highly desirable to preserve ease of usage
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Summary

HTM is not a silver bullet

  • Shines with short infrequent transactions and concurrent data structures
  • Great in energy efficiency and at low thread count
  • Hyper-threading amplifies HTM’s inherent limitations
  • HTM requires careful tuning of parameters governing the fallback:
  • automatic tuning is highly desirable to preserve ease of usage

STM performs best on average

  • …and with applications with complex transactions
  • Its energy efficiency tends to be worse than HTM
  • Compiler instrumentation has room for improvement
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Summary

HTM is not a silver bullet

  • Shines with short infrequent transactions and concurrent data structures
  • Great in energy efficiency and at low thread count
  • Hyper-threading amplifies HTM’s inherent limitations
  • HTM requires careful tuning of parameters governing the fallback:
  • automatic tuning is highly desirable to preserve ease of usage

STM performs best on average

  • …and with applications with complex transactions
  • Its energy efficiency tends to be worse than HTM
  • Compiler instrumentation has room for improvement

HybridTMs are not there yet

  • Need better support from hardware
  • Can we do better without it?