Via Resistance Variation-Aware Static Timing Analysis Moonsu Kim, - - PowerPoint PPT Presentation

Via Resistance Variation-Aware Static Timing Analysis

Moonsu Kim, Seungjae Jung, Jaehong Park, Junsu Kim, Naya Ha, Sunik Heo, Kyungtae Do, Jungyun Choi, Nathaniel Conos*, Kelvin Le*, Hanif Fatemi* Design Technology, Foundry, Samsung Electronics, South Korea; *Design Group, Synopsys Inc, United States of America

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Introduction

▸ Statistical STA is accurate but has big overhead ▸ Parametric OCV and LVF models are good for cell ▸ Wire/VIA resistance variation becomes significant

• Big impact on timing for high-performance chip

▸ POCV-like technology is developed for VIA variation

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Background

▸ Global, Systematic and Local variations

• Global: wafer-to-wafer, die-to-die
• Local: within die local random variations

▸ Timing models for different variation

• Global: corner based approach
• Local: flat derating, AOCV, POCV/LVF

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Via Resistance Variation Modeling

▸ Local via variation is observed to be independent from each other ▸ Local via variation can be extracted from total and global variation

• Total/Global variation from Silicon
• Local variation from statistical subtraction

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Via Resistance Mismatch

Via Resistance Variation aware STA Flow

▸ Two-corner parasitic data is extracted from star-RC with GPD format

• Via Min/Via Max corner are different
• All other R/C/CC are the same

▸ Primetime perform statistical timing analysis

• Local Via variation extracted from two corners

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Via Resistance Variation-aware Delay Computation

▸ Compute via variation impact on cell and wire delay and transition time

• Cell and wire delay are correlated through via

variations

▸ Combine cell and wire delay distributions ▸ Compute receiver transition time variations

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Experiment Results

▸ Good accuracy correlation is observed compared with MC ▸ Competitive performance overhead compared with base STA

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Accuracy and Performance Overhead

Design # of instances (in K) Run Time Overhead Peak Memory Overhead 1 145 1.0 1.1 2 136 1.0 1.0 3 1564 1.2 1.0 4 1230 1.1 1.1 5 1557 1.2 1.0 6 345 1.1 1.1 7 831 1.1 1.1 8 36 1.0 1.0 9 11 1.0 1.0 10 2045 1.1 1.2 1.1 1.1 Average

Experiment Results

▸ Pessimism reduction benefit is observed by comparing with corner STA

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Pessimism Reduction

case1 case2 case3 case4 global only

• 6.44%
• 6.68%
• 7.20%
• 7.96%

global + local

• 5.74%
• 5.94%
• 6.41%
• 7.08%

global only

• 4.49%
• 4.66%
• 5.02%
• 5.58%

global + local

• 3.91%
• 4.06%
• 4.38%
• 4.86%

Average of relative path delay difference [%]

mode voltage corner High Less High

Summary

▸ Via resistance is expected to increase rapidly when process continues to scale down ▸ A practical statistical timing analysis method is developed for via resistance variation ▸ Enables timing analysis to be analyzed with appropriate process variation impact of via resistance variation ▸ Great collaboration between Foundry and EDA company

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