The SLAC KPiX Chip for ILC K p f GEM-Digital Hadron C l - - PowerPoint PPT Presentation

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The SLAC KPiX Chip for ILC K p f GEM-Digital Hadron C l - - PowerPoint PPT Presentation

May 17, 2023 146 likes •419 views

The SLAC KPiX Chip for ILC K p f GEM-Digital Hadron C l Calorimetry i t A d Andy White Whit for the GEM-DHCAL Group for the GEM-DHCAL Group (UTA UW CNU) ( ) With many thanks to SLAC colleagues: M. Breidenbach, G. Haller, D.

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SLIDE 1

The SLAC KPiX Chip for ILC K p f GEM-Digital Hadron C l i t Calorimetry

A d Whit Andy White for the GEM-DHCAL Group for the GEM-DHCAL Group (UTA – UW – CNU) ( )

With many thanks to SLAC colleagues:

RD51 P O b 2008

  • M. Breidenbach, G. Haller, D. Freytag, R. Herbst

RD51, Paris, October 2008

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SLIDE 2

GEM/DHCAL active layer concept

  • 2100V

∆V ~400V ∆V ~400V ∆V ~400V 0V 0V

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SLIDE 3

KPiX chip One channel of 1024 Dynamic gain

KPiX/GEM/DHCAL

DHCAL

Dynamic gain select 13 bit A/D

anode pad

A/D

Storage until end of train. Leakage current end of train. Pipeline depth presently is 4

Event trigger

subtraction

calibration

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SLIDE 4

GEM-DHCAL/KPiX boards with Interface and FPGA boards

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SLIDE 5

Redesigned chamber – all fishing line spacer

  • KPiX anode board with extra electronics protection

/ d fl h h

  • Better/more direct gas flow through ionization gap
  • No large dielectric spacer(s) – previously killed

g p p y signal

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SLIDE 6

GEM chamber with KPiX v4 – early 2008

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SLIDE 7

GEM + KPiX long source run at SLAC

nnel # fC Cha f Channel # Channel #

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SLIDE 8

GEM + KPiX response in lab at SLAC

Away from the source Right under the source Away from the source Right under the source Away from the source Right under the source

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SLIDE 9

First results from new GEM chamber + KPiX

fC scale fC scale

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SLIDE 10

UTA 75hr Long run at SLAC

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SLIDE 11

GEM/DHCAL ith KPiX d t GEM/DHCAL with KPiX readout

  • Due to the synchronous design of KPiX, data taking

efficiency was low with (asynchronous) source. y ( y )

  • KPiX v7 offers new timing flexibility.

W iti f 7 t d d t l bt ti t

  • Waiting for v7 -> study pedestal subtraction to

(eventually) extract MIP distribution

  • Also study channel variation/stability of calibration and

pedestal feedback to SLAC KPiX developers.

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SLIDE 12

Calibration studies with KPiX v4

Goals: Goa s

  • understand relation between pedestal distribution and

“zero-charge” injected distribution zero charge injected distribution.

  • investigate stability of gain, response to injected

charge pedestals > subtraction of noise to yield MIP charge, pedestals -> subtraction of noise to yield MIP signals. d st d f t s th t i fl i t ( h l

  • understand factors that influence gain etc. (channel

to channel, single channel/environment, long-term fluctuations fluctuations…

  • ultimately – develop calibration procedure (how often,

length of calibration/pedestal runs ) length of calibration/pedestal runs,…)

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SLIDE 13

KPiX injected charge calibration K j g

Internal capacitor charged via DAC, readout through d t th data path

  • > measure gain from slope
  • > measure “zero-injected charge” response, “Y-int”
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SLIDE 14

Initial Calibration Analysis Example Initial Calibration Analysis Example

  • Two Calib Data Sets

– 19 hr run starting in evening – weekend – g g 6/28 – 24 hr run starting in morning - work week – 24 hr run starting in morning work week 7/01

  • Each Channel’s Pedestal Mean Sigma; Gain
  • Each Channel s Pedestal Mean, Sigma; Gain,

and Y-Intercept verses Run# (on order of an hour) is graphed for each channel and fit with a hour) is graphed for each channel and fit with a straight line.

Work of UTA Master’s student Jacob Smith

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SLIDE 15

Normal Ped Sig Gain Y-int One channel KPiX v4 Double 16 17 19 18

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SLIDE 16

Normal Ped Sig Gain Y-int Double 19hr

Weekend run

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SLIDE 17

Normal Ped Sig Gain Y-int Double 24hr

Weekday run

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SLIDE 18

Normal Ped Sig Gain Y-int Double April - June

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SLIDE 19
  • Issue with KPiX v4 triggering mode:

GEM/KPiX source data taking gg g

  • “forced trigger” (software) mode was used – no fixed

time relation between arrival of electron from source t m r at on tw n arr a of ctron from sourc and internal timing of KPiX.

  • we suspect that a reset is responsible for incomplete

we suspect that a reset is responsible for incomplete integration of the charge this would distort MIP (Landau) distribution by

  • this would distort MIP (Landau) distribution by

lowering ADC values

  • also noise peak wider with

data than for pedestal runs data than for pedestal runs

  • > working on understanding

this effect. this effect.

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SLIDE 20

Next step: KPiX v7

KPiX is a synchronous device – tied to ILC beam timing

  • > problem being efficient in an asynchronous
  • > problem being efficient in an asynchronous

environment e.g. MTBF , cosmics, or source(s). > KPiX v4 was only ≤5% efficient for source or

  • > KPiX v4 was only ≤5% efficient for source or

asynchronous beam. KPiX 7 ll fl ibilit i ti i dj t t

  • > KPiX v7 allows more flexibility in timing adjustments –

via slowing down the master clock - should provide data taking efficiencies in 40-50% range in an asynchronous taking efficiencies in 40-50% range in an asynchronous environment, and has new reset scheme. First version of v7 now at UTA plus we have a new

  • First version of v7 now at UTA, plus we have a new

anode board designed to work with it. I iti l t t lib ti ith i j t d h

  • Initial tests -> calibration with injected charge

(internal) -> results.

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SLIDE 21

New KPiX Board for v7 New KPiX Board for v7

  • 1. The KPiX chip is located just next to the PAD area.
  • 2. 310 x 310 mm. with 8 x 8cm. pad area at the center

p with 0.2mm. Gaps between pads.

  • 3. Surface mount parts (connectors...). Nothing will be

n th PAD sid

  • n the PAD side.
  • 4. All the holes filled for gas tightness.

5 Leaving about 1" space on the edges for sealing

  • 5. Leaving about 1 space on the edges for sealing....
  • 6. KPiX board thicker, flatter…
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SLIDE 22

KPiX v7 board layout

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SLIDE 23
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SLIDE 24

KPiX v7 – first calibration results

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SLIDE 25

KPiX v7 chamber plans KPiX v7 chamber plans

  • New v7 chamber works well – stable (no trips) over

several weeks so far.

  • Verify new software for v7
  • Operate v7 with new GEM chamber (in progress)

Operate v7 with new GEM chamber (in progress)

  • Complete calibration/understand behavior with v7
  • Work with SLAC to achieve 40-50% efficiency in

cosmic and source data taking.

  • Work at UTA and SLAC.
  • Take beam data at MTBF CERN?

Take beam data at MTBF, CERN?

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SLIDE 26

Future Plans for GEM/DHCAL

  • Complete GEM chamber studies with v7
  • Construct ~1m x 0 3m chamber
  • Construct ~1m x 0.3m chamber
  • Construct ~ 1m2 plane(s).
  • Issue with foil supplier: 3M closed plant in Missouri
  • Have obtained quotes from CERN for 99cm x 32cm

Have obtained quotes from CERN for 99cm x 32cm foils.

  • Alternative: Thick-GEM chamber – if large areas are
  • Alternative: Thick-GEM chamber if large areas are

viable LCDRD Supplement 2nd year minimal amount to

  • LCDRD Supplement, 2nd year – minimal amount to

purchase foils + limited postdoc support. Att ti t 1

2

l d i ll /thi k

  • Attention to 1m2 plane design – walls/thickness, gas

supply, KPiX readout… >>>

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SLIDE 27

Future Plans for GEM/DHCAL Future Plans for GEM/DHCAL

  • Next generation KPiX (256 1024 channels)

Next generation KPiX (256…1024 channels)

  • Note: started out to test GEM with both KPiX and

DCAL chips we would like to continue this also DCAL chips – we would like to continue this…also perhaps use alternative readout from Europe W ill h i it j i i i N b

  • …We will have a visitor joining our group in November –

much experience with detectors/readout % %

  • We also will be hiring a postdoc 50% ILC R&D, 50%

ATLAS