SLIDE 6 Marcello Mannelli
The evolution of Vertex Detectors The evolution of Vertex Detectors
Siena October 2001
PI XEL CHI P WI TH FI NAL ARCHI TECTURE: CMS PI XEL CHI P WI TH FI NAL ARCHI TECTURE: CMS
( submitted Aug. / Sept 2000 in DMI LL ) ( submitted Aug. / Sept 2000 in DMI LL )
- ~50% pixels of f inal 52x53 pixel ROC
~50% pixels of f inal 52x53 pixel ROC
f inal Column Drain Architecture Column Drain Architecture
- f ast hit scanning mechanism (>GHz)
f ast hit scanning mechanism (>GHz)
- double hit capability during DC scan
double hit capability during DC scan
f inal Double Column Periphery Double Column Periphery
- 8 timestamp buf f ers / double column
8 timestamp buf f ers / double column
- 24 pixel data buf f er / double column
24 pixel data buf f er / double column
- test chip with 36x40 pixels (~240K transistors)
test chip with 36x40 pixels (~240K transistors)
- L1 trigger delay up to 255 bunch crossing
L1 trigger delay up to 255 bunch crossing
f inal Analog Readout Chain Analog Readout Chain
- 6 clock cycles per pixel hit
6 clock cycles per pixel hit
- analog coded column & pixel address
analog coded column & pixel address
- analog readout of pixel pulse height
analog readout of pixel pulse height
missing Control & I nterf ace Block Control & I nterf ace Block !! !!
DAC’s, Voltage Regulators, f ast I 2C etc. , Voltage Regulators, f ast I 2C etc. DM_PSI 41