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The Associative Memory system for the FTK processor at ATLAS Daniel Magalotti University of Modena and Reggio Emilia 114th ICATPP Conference on Astroparticle, Particle, Space Physics and Detectors for Physics Applications 23-27 September

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Daniel Magalotti – University of Modena and Reggio Emilia

The Associative Memory system for the FTK processor at ATLAS

114th ICATPP Conference on Astroparticle, Particle, Space Physics and Detectors for Physics Applications 23-27 September 2013, Como

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 Fast TracKer (FTK): On-line tracker for Atlas upgrade  FTK architecture: description of the Associative Memory

system

 Result of the prototypes testing  High speed links testing  Pattern Matching in the AM chip  Crate cooling test  Evolution of the AM system  Conclusion

Outline

Daniel Magalotti - 24/09/2013 2

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 FTK reconstructs charged particles

trajectories in the silicon detector (Pixel & SCT) at “1.5 trigger level”.

 Extremely difficult task 100kHz

processing rate ~70 overlapping events (pile-up) at highest luminosity.

Daniel Magalotti - 24/09/2013 3

An online silicon detector tracker for the ATLAS upgrade

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 FTK reconstructs charged particles

trajectories in the silicon detector (Pixel & SCT) at “1.5 trigger level”.

 Extremely difficult task 100kHz

processing rate ~70 overlapping events (pile-up) at highest luminosity.

An online silicon detector tracker for the ATLAS upgrade

Daniel Magalotti - 24/09/2013 4

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SLIDE 5

FTK

“1.5 Level Trigger processor”

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 Silicon data currently used only locally (ROI) and late in Level 2.  FTK reconstructs all tracks with PT>1 GeV/c in time for Level 2.  Track parameters are computed with full detector resolution.

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SLIDE 6

FTK: Pattern matching & track fitting

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Road = Low resolution Track

Comparison

Road = Low resolution Track Road = Low resolution Track p-p p-p

 Pattern Bank: All the possible patterns (low resolution real track

candidates) are pre-calculated and stored in the Pattern Bank.

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SLIDE 7

 Pattern Bank: All the possible patterns (low resolution real track

candidates) are pre-calculated and stored in the Pattern Bank.

 Pattern matching: All the hits in each event are compared with all

the patterns in the Bank and track candidates (ROADs) are found.

FTK: Pattern matching

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Comparison

p-p p-p p-p AMChip

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SLIDE 8

FTK: Track Fitting

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Road = Low resolution Track

Comparison

Road = Low resolution Track Road = Low resolution Track p-p p-p

 Pattern Bank: All the possible patterns (low resolution real track

candidates) are pre-calculated and stored in the Pattern Bank.

 Pattern matching: All the hits in each event are compared with all

the patterns in the Bank and track candidates (ROADs) are found.

 Track Fitting: Fits of the full resolution silicon HITs contained in

each ROAD determine particle tracks parameters.

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SLIDE 9

FTK Processor Unit

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  • Processing Unit: 9U VME board (AMB-FTK) + large Rear card (AUX

Card) + 4 little mezzanines (LAMB-FTK)

  • Global processor is composed from 8 VME crate and 5 ACTA crate
  • Silicon HITs relative to events accepted by Level 1 (~100kHz) are

distributed to all AMChips.

  • 1 HIT is compared with ~ 8x10^6 of Precalculated pattern.

AUX-Board LAMB-FTK

Pattern matching

AMB-FTK

Track fitting (first stage)

ERNI high speed connector (data I/O)

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SLIDE 10

AM System Logic

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AMBFTK board LAMBFTK board

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SLIDE 11

AM System Logic

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INPUT FPGAs

Input FPGAs: Xilinx Spartan6 with Low Power Gigabit Transceiver (GTP) 4 parallel buses @ 100MHz 4 serial buses @ 2Gbps

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SLIDE 12

AM System Logic

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OUTPUT FPGAs

Input FPGAs: Xilinx Spartan6 with Low Power Gigabit Transceiver (GTP) 4 parallel buses @ 100MHz 4 serial buses @ 2Gbps Output FPGAs: Xilinx Spartan6 with Low Power Gigabit Transceiver (GTP) 4 serial buses @ 2Gbps from each LAMB

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AM System Logic

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CONTROL FPGA

Input FPGAs: Xilinx Spartan6 with Low Power Gigabit Transceiver (GTP) 4 parallel buses @ 100MHz 4 serial buses @ 2Gbps Output FPGAs: Xilinx Spartan6 with Low Power Gigabit Transceiver (GTP) 4 serial buses @ 2Gbps from each LAMB Control FPGAs: A simple Finite State Machine

Wait End Event Send INIT EVENT

Wait for all End Event from input HIT buses and

  • utput ROAD buses

Initialization of the AMChip to receive the next event

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Serial Link Test: Hit input and Road Output

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Serial Link 2 Gbit/s TX-FPGA RX-FPGA The serial link characterization and testing

 Simulation of the line with the SigXplore Cadence  Evaluation of the quality of the link with Pseudo Random Bit

Sequence (PRBS)

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SLIDE 15

Serial Link Test: Hit input and Road Output

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Serial Link 2 Gbit/s TX-FPGA RX-FPGA The serial link characterization and testing

 Simulation of the line with the SigXplore Cadence  Evaluation of the quality of the link with Pseudo Random Bit

Sequence (PRBS)

Bit Error Rate BER< 10-10

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AMChips configuration

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VME

  • The AMChip are accessible via JTAG protocol => a dedicated FPGA

perform the VME-JTAG conversion

  • The JTAG controller of the all AMChips is controlled in parallel with

several VME access.

8 pipeline of 4 AMChips of JTAG chain for each LAMB

L_ADDR[2:0] WRPAM

VME INTERFACE FPGA

BSCAN LAMB

RBSCAN

JTAG AMChips x32

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AMChips configuration

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VME

  • The AMChip are accessible via JTAG protocol => a dedicated FPGA

perform the VME-JTAG conversion

  • The JTAG controller of the all AMChips is controlled in parallel with

several VME access.

  • The simulated pattern bank is loading in all AMChips => a check

pattern operation to show the successful of pattern loading

8 pipeline of 4 AMChips of JTAG chain for each LAMB

x32

CHECH patten result

The Pattern Bank file and the Check Pattern file have the same pattern All the pattern have been loaded perfectly

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Data flow testing (step 1)

  • Simulate silicon HITS Input to generate a file
  • Silicon HITS Input are loaded into the inputs FPGAs memory (red

square) through VME.

  • When the memory are all loaded, the FPGAs transmit data to he

LAMBs at full speed.

Data flow testing: input HIT distribution

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VME

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SLIDE 19

Data flow testing: output ROADS collection

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VME

Data flow testing (step 2)

  • After the all HITS is received from the all AMChips we send and INIT

EVENT signal so the matched road can go out

  • The road at full speed is Collected in the Output FPGAs (blue squares)

Data flow testing (step 3)

  • The road is stored in memories that are read from VME and saved in a

file

  • Compare Hardware and Simulation output files

The simulated ROADs and the matched ROADs have about the same road. Pattern matching error rate 1 pattern error/ 1000 events

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Cooling Tests

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Expected power consumption

  • 1 Processing unit ~ 300 W
  • 16 PUs in a single VME crate
  • ~ 5 kW per crate.

Power supply voltages for the FTK system:

 5V  3,3V  1,2V

Need Cooling test!

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Cooling Tests without chiller

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U F U R U C L C L F L R

 Cooling test currently in

progress INFN PAVIA.

 Power consumption simulated

with resistors.

 Six sensor used to measure the

temperature in the crate (red circles)

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SLIDE 22

WEINER and CDF fan result

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The temperature has a peak of in the upper side of crate.

WEINER fan unit CDF fan unit

Temperature is in the range of 40-60°C degrees.

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Evolution of the AM system

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Evolution of the AMBoard: AMBSLP processor

INPUT FPGAs OUTPUT FPGAs

No parallel buses for HIT distribution Only serial links connection

  • 12 links for the

HITs @ 2Gbps

  • 16 links for the

ROADs @ 2Gbps

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SLIDE 24

Evolution of the AM system

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New LAMBSLP:

  • Simplified routing
  • LAMBSLP reduced size no FPGAs

Evolution of the mezzanine LAMB: LAMBSLP

Old LAMB problem:

  • high density of connection
  • high number of devices for fan-out
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Conclusion

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 We have described the FTK processing unit referring in particular to the

AM system for the pattern matching function

 We have shown the result of the tests of the AM system

 The serial link connections are very good quality for the 2Gbps rate  The results of the pattern matching test show that all complete system works

very well.

 We have show the cooling test with the power consumption of the

finale system

 We have described the evolution of the AM system with only serial link

connections (AMBSLP)

 All the previous tests have to be perform also for this one system

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Thank You!

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