Techniques et outils pour la vrification de systmes-sur-puces au - - PowerPoint PPT Presentation

SoC LusSy PINAPA BISE Conclusion

Techniques et outils pour la vérification de systèmes-sur-puces au niveau transactionnel

Matthieu Moy

Synchronous Languages and Reactive Systems Laboratoire Verimag, INPG System Platform Group STMicroelectronics

9 Décembre 2005

Jury: Gérard Michel Président Stephen Edwards Rapporteur Jean-Pierre Talpin Rapporteur Florence Maraninchi Directrice Laurent Maillet-Contoz Examinateur Matthieu Moy (Verimag/STMicroelectronics) Soutenance de Thèse 9 Décembre 2005 < 1 / 49 >

SoC LusSy PINAPA BISE Conclusion

Techniques and Tools for the Verification of Systems-on-a-Chip at the Transaction Level

Matthieu Moy

Synchronous Languages and Reactive Systems Verimag Laboratory, INPG System Platform Group STMicroelectronics

December 9th, 2005

Jury: Gérard Michel President Stephen Edwards Reviewer Jean-Pierre Talpin Reviewer Florence Maraninchi Director Laurent Maillet-Contoz Examiner Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 2 / 49 >

SoC LusSy PINAPA BISE Conclusion

Objective of the Thesis

“Provide a connection from SystemC/TLM to existing verification tools”

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 3 / 49 >

SoC LusSy PINAPA BISE Conclusion

Outline

1

Context: Embedded Systems and Systems-on-a-Chip

2

LUSSY: A Toolbox for the Analysis of Systems-on-a-Chip at the Transaction Level

3

PINAPA: Syntax and Architecture Extraction

4

BISE: Semantic Extraction

5

Conclusion

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 4 / 49 >

SoC LusSy PINAPA BISE Conclusion

Outline

1

Context: Embedded Systems and Systems-on-a-Chip

2

LUSSY: A Toolbox for the Analysis of Systems-on-a-Chip at the Transaction Level

3

PINAPA: Syntax and Architecture Extraction

4

BISE: Semantic Extraction

5

Conclusion

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 5 / 49 >

SoC LusSy PINAPA BISE Conclusion

The Design Gap

Transistors on a circuit (log scale) 1990 1995 2000 2005 Years 1,000,000,000 100,000,000 1,000,000 10,000,000 +30%/year Designers productivity 20%/year Design gap Physical capacity +50%/year

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 6 / 49 >

SoC LusSy PINAPA BISE Conclusion

Hardware Vs Software

Hardware

◮ Fast ◮ Power-efficient

Software

◮ Flexible ◮ Reusable ◮ Faster to write Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 7 / 49 >

SoC LusSy PINAPA BISE Conclusion

Hardware-Software Partitioning

non-programmable ASIC: 100% Hardware General-purpose processors: 100% Software Systems-on-a-Chip (SoC): Mixture of Hardware and Software designed for each other

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 8 / 49 >

SoC LusSy PINAPA BISE Conclusion

SoC Design Flow

Time

Traditional Design Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 9 / 49 >

SoC LusSy PINAPA BISE Conclusion

SoC Design Flow

Time

Traditional Design Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation 1,000,000 $ !! Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 9 / 49 >

SoC LusSy PINAPA BISE Conclusion

SoC Design Flow

Time

Traditional Design Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

TLM Enhancement

Specification, Algorithm RTL Design Synthesis Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 9 / 49 >

SoC LusSy PINAPA BISE Conclusion

SoC Design Flow

Time

Traditional Design Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

TLM Enhancement

Specification, Algorithm RTL Design Synthesis Software Development Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 9 / 49 >

SoC LusSy PINAPA BISE Conclusion

SoC Design Flow

Time

Traditional Design Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

TLM Enhancement

Specification, Algorithm RTL Design Synthesis Software Development TLM Model Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 9 / 49 >

SoC LusSy PINAPA BISE Conclusion

SoC Design Flow

Time

Traditional Design Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

TLM Enhancement

Specification, Algorithm RTL Design Synthesis Software Development TLM Model Integration Factory Validation Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 9 / 49 >

SoC LusSy PINAPA BISE Conclusion

SoC Design Flow

Time

Traditional Design Flow

Specification, Algorithm RTL Design Synthesis Factory Software Development Integration Validation

TLM Enhancement

Specification, Algorithm RTL Design Synthesis Software Development TLM Model Integration Factory Validation

gain

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 9 / 49 >

SoC LusSy PINAPA BISE Conclusion

The Transaction Level Model: Principles and Objectives

A high level of abstraction, that appear early in the design-flow

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 10 / 49 >

SoC LusSy PINAPA BISE Conclusion

The Transaction Level Model: Principles and Objectives

A high level of abstraction, that appear early in the design-flow A virtual prototype of the system, to enable

◮ Early software development ◮ Architecture exploration ◮ Integration of components

Abstract communication protocols and micro-architecture (remove implementation details from RTL)

◮ Fast simulation (≃ 1000x faster than RTL) ◮ Lightweight modeling effort (≃ 10x less than RTL) Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 10 / 49 >

SoC LusSy PINAPA BISE Conclusion

The Transaction Level Model: Traces

TLM: Transaction Level Model RTL: Register Transfer Level

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 11 / 49 >

SoC LusSy PINAPA BISE Conclusion

An Example TLM Model

Components CPU RAM ROM IC

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 12 / 49 >

SoC LusSy PINAPA BISE Conclusion

An Example TLM Model

Components CPU RAM ROM IC Abstract channel Interrupt signal Ports

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 12 / 49 >

SoC LusSy PINAPA BISE Conclusion

An Example TLM Model

Components CPU RAM ROM IC Abstract channel Interrupt signal Ports Processes

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 12 / 49 >

SoC LusSy PINAPA BISE Conclusion

An Example TLM Model in SystemC

Components CPU RAM ROM IC Abstract channel Interrupt signal Ports Processes C++ code SystemC + constructs

bool var; ... var = true; ... port.write(var); ...

TAC channel

... ... } if (p.read()) {

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 12 / 49 >

SoC LusSy PINAPA BISE Conclusion

SystemC

Useful to write Transaction Level Models

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 13 / 49 >

SoC LusSy PINAPA BISE Conclusion

SystemC

Useful to write Transaction Level Models Library for C++ (⇒ compilable with any C++ compiler) Provides

◮ Some objects usable directly (sc_signal, sc_event, . . . ) ◮ Some base classes to be implemented (sc_module, . . . ) ◮ An execution kernel (including a scheduler) Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 13 / 49 >

SoC LusSy PINAPA BISE Conclusion

Why SystemC?

For the industry:

◮ Good support for TLM and heterogeneous systems ⋆ Simulates fast ⋆ Hardware/Software ⋆ TLM/RTL/Gate-level ◮ Many available tools ⋆ from CAD vendors ⋆ usual tools for C++ (debuggers, editors, lint, profilers, . . . ) Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 14 / 49 >

SoC LusSy PINAPA BISE Conclusion

Why SystemC?

For the industry:

◮ Good support for TLM and heterogeneous systems ⋆ Simulates fast ⋆ Hardware/Software ⋆ TLM/RTL/Gate-level ◮ Many available tools ⋆ from CAD vendors ⋆ usual tools for C++ (debuggers, editors, lint, profilers, . . . )

As a research objective:

◮ Used in the industry ◮ Many case-studies available (no need to translate them) ◮ Work on a portion of the real design-flow Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 14 / 49 >

SoC LusSy PINAPA BISE Conclusion

Transaction Level Modeling in SystemC

SystemC provides the building blocks, but no high-level bus model Additional components are needed for TLM channels

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 15 / 49 >

SoC LusSy PINAPA BISE Conclusion

Transaction Level Modeling in SystemC

SystemC provides the building blocks, but no high-level bus model Additional components are needed for TLM channels STMicroelectronics developed several bus models

◮ BASIC: an example channel ◮ TAC: a TLM channel used in production

Will hopefully be standardized

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 15 / 49 >

SoC LusSy PINAPA BISE Conclusion

Execution of a SystemC Program

Architecture and Behavior

◮ No specific architecture description language ◮ Arbitrary C++ can be used for both aspects Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 16 / 49 >

SoC LusSy PINAPA BISE Conclusion

Execution of a SystemC Program

Architecture and Behavior

◮ No specific architecture description language ◮ Arbitrary C++ can be used for both aspects

Elaboration phase

◮ Instantiate the components ◮ Bind them together

Simulation

◮ Run the processes one by one ◮ With a fixed architecture Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 16 / 49 >

SoC LusSy PINAPA BISE Conclusion

An Example TLM Model in SystemC

Components CPU RAM ROM IC Abstract channel Interrupt signal Ports Processes C++ code SystemC + constructs

bool var; ... var = true; ... port.write(var); ...

TAC channel

... ... } if (p.read()) {

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 17 / 49 >

SoC LusSy PINAPA BISE Conclusion

Elaboration Phase: Build Architecture

int sc_main(int argc, char ** argv) { irq_controler * ic = new irq_controler("IRQ"); cpu * cpu = new cpu("CPU0"); ram * ram = new ram("INT_RAM"); rom * rom = new rom("ROM"); tac_channel * channel = new tac_channel("CHANNEL"); sc_signal<bool> sig; cpu->master_port.bind(channel->slave_port); ic->slave_port.bind(channel->master_port); ram->slave_port.bind(channel->master_port); rom->slave_port.bind(channel->master_port); ic->port.bind(sig); cpu->p.bind(sig); sc_start(); }

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 18 / 49 >

SoC LusSy PINAPA BISE Conclusion

Elaboration Phase: Build Architecture

// Main function int sc_main(int argc, char ** argv) { irq_controler * ic = new irq_controler("IRQ"); cpu * cpu = new cpu("CPU0"); ram * ram = new ram("INT_RAM"); rom * rom = new rom("ROM"); tac_channel * channel = new tac_channel("CHANNEL"); sc_signal<bool> sig; cpu->master_port.bind(channel->slave_port); ic->slave_port.bind(channel->master_port); ram->slave_port.bind(channel->master_port); rom->slave_port.bind(channel->master_port); ic->port.bind(sig); cpu->p.bind(sig); sc_start(); }

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 18 / 49 >

SoC LusSy PINAPA BISE Conclusion

Elaboration Phase: Build Architecture

int sc_main(int argc, char ** argv) { // Components Instantiation (creation of C++ objects) irq_controler * ic = new irq_controler("IRQ"); cpu * cpu = new cpu("CPU0"); ram * ram = new ram("INT_RAM"); rom * rom = new rom("ROM"); tac_channel * channel = new tac_channel("CHANNEL"); sc_signal<bool> sig; cpu->master_port.bind(channel->slave_port); ic->slave_port.bind(channel->master_port); ram->slave_port.bind(channel->master_port); rom->slave_port.bind(channel->master_port); ic->port.bind(sig); cpu->p.bind(sig); sc_start(); }

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 18 / 49 >

SoC LusSy PINAPA BISE Conclusion

Elaboration Phase: Build Architecture

int sc_main(int argc, char ** argv) { irq_controler * ic = new irq_controler("IRQ"); cpu * cpu = new cpu("CPU0"); ram * ram = new ram("INT_RAM"); rom * rom = new rom("ROM"); tac_channel * channel = new tac_channel("CHANNEL"); sc_signal<bool> sig; // Binding (link between objects) cpu->master_port.bind(channel->slave_port); ic->slave_port.bind(channel->master_port); ram->slave_port.bind(channel->master_port); rom->slave_port.bind(channel->master_port); ic->port.bind(sig); cpu->p.bind(sig); sc_start(); }

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 18 / 49 >

SoC LusSy PINAPA BISE Conclusion

Elaboration Phase: Build Architecture

int sc_main(int argc, char ** argv) { irq_controler * ic = new irq_controler("IRQ"); cpu * cpu = new cpu("CPU0"); ram * ram = new ram("INT_RAM"); rom * rom = new rom("ROM"); tac_channel * channel = new tac_channel("CHANNEL"); sc_signal<bool> sig; cpu->master_port.bind(channel->slave_port); ic->slave_port.bind(channel->master_port); ram->slave_port.bind(channel->master_port); rom->slave_port.bind(channel->master_port); ic->port.bind(sig); cpu->p.bind(sig); // Start simulation (let the kernel execute processes) sc_start(); }

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 18 / 49 >

SoC LusSy PINAPA BISE Conclusion

Outline

1

Context: Embedded Systems and Systems-on-a-Chip

2

LUSSY: A Toolbox for the Analysis of Systems-on-a-Chip at the Transaction Level

3

PINAPA: Syntax and Architecture Extraction

4

BISE: Semantic Extraction

5

Conclusion

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 19 / 49 >

SoC LusSy PINAPA BISE Conclusion

Importance of TLM in the design flow

No automatic synthesis from TLM to RTL A complement for RTL (not a replacement)

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 20 / 49 >

SoC LusSy PINAPA BISE Conclusion

Importance of TLM in the design flow

No automatic synthesis from TLM to RTL A complement for RTL (not a replacement) TLM serves as a reference model for RTL validation Embedded software is developed and tested partly on the TLM model

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 20 / 49 >

SoC LusSy PINAPA BISE Conclusion

Importance of TLM in the design flow

No automatic synthesis from TLM to RTL A complement for RTL (not a replacement) TLM serves as a reference model for RTL validation Embedded software is developed and tested partly on the TLM model ⇒ Although TLM models are not embedded in the chip, their validation is important

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 20 / 49 >

SoC LusSy PINAPA BISE Conclusion

State of the Art

Semantics of SystemC

◮ Several papers for a semantics of RTL SystemC (very strict subset) ◮ Usually do not take into account the real semantics of the scheduler

Verification of TLM models

◮ Recent research area ◮ Almost nothing relevant when we started Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 21 / 49 >

SoC LusSy PINAPA BISE Conclusion

State of the Art

Semantics of SystemC

◮ Several papers for a semantics of RTL SystemC (very strict subset) ◮ Usually do not take into account the real semantics of the scheduler

Verification of TLM models

◮ Recent research area ◮ Almost nothing relevant when we started

In the meantime ...

◮ Several tools for SystemC (front-ends, verification, lint, . . . ) ◮ Published work usually target a lower abstraction level than TLM as

we use it in STMicroelectronics

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 21 / 49 >

SoC LusSy PINAPA BISE Conclusion

Objectives of the Thesis

“Provide a connection from SystemC/TLM to existing verification tools”

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 22 / 49 >

SoC LusSy PINAPA BISE Conclusion

Objectives of the Thesis

“Provide a connection from SystemC/TLM to existing verification tools”

Main difficulties

◮ TLM mixes hardware and software

⇒ Verification is undecidable

◮ Abstractions will have to be made Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 22 / 49 >

SoC LusSy PINAPA BISE Conclusion

Objectives of the Thesis

“Provide a connection from SystemC/TLM to existing verification tools”

Main difficulties

◮ TLM mixes hardware and software

⇒ Verification is undecidable

◮ Abstractions will have to be made

Main choices

◮ Deal with real SystemC code ◮ Fully automated tool-chain ◮ As few abstractions as possible Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 22 / 49 >

SoC LusSy PINAPA BISE Conclusion

Objectives of the Thesis

“Provide a connection from SystemC/TLM to existing verification tools”

Main difficulties

◮ TLM mixes hardware and software

⇒ Verification is undecidable

◮ Abstractions will have to be made

Main choices

◮ Deal with real SystemC code ◮ Fully automated tool-chain ◮ As few abstractions as possible

Consequences

◮ We need a front-end to read the SystemC code ◮ We need a semantics for SystemC

⇒ Formal, Simple, Executable

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 22 / 49 >

SoC LusSy PINAPA BISE Conclusion

Expressing properties

Safety properties only (as opposed to liveness)

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 23 / 49 >

SoC LusSy PINAPA BISE Conclusion

Expressing properties

Safety properties only (as opposed to liveness) No new specific language Express properties in C++/SystemC

◮ ASSERT(x.read() == true) Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 23 / 49 >

SoC LusSy PINAPA BISE Conclusion

Expressing properties

Safety properties only (as opposed to liveness) No new specific language Express properties in C++/SystemC

◮ ASSERT(x.read() == true)

Use generic properties (things that you usually don’t want)

◮ Global dead-lock ◮ Multiple write on a sc_signal ◮ Process termination ◮ Mutual exclusion Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 23 / 49 >

SoC LusSy PINAPA BISE Conclusion

The LUSSY Tool Chain

Transformations Abstract Format (in memory) Concrete Format (file) External tools/formats SystemC Verification tool Property

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 24 / 49 >

SoC LusSy PINAPA BISE Conclusion

The LUSSY Tool Chain

Transformations Abstract Format (in memory) Concrete Format (file) External tools/formats SystemC Verification tool tool-specific format Property

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 24 / 49 >

SoC LusSy PINAPA BISE Conclusion

The LUSSY Tool Chain

Transformations Abstract Format (in memory) Concrete Format (file) External tools/formats SystemC Pinapa Verification tool tool-specific format Property

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 24 / 49 >

SoC LusSy PINAPA BISE Conclusion

The LUSSY Tool Chain

Transformations Abstract Format (in memory) Concrete Format (file) External tools/formats SystemC Abstract SystemC Pinapa Verification tool tool-specific format Property

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 24 / 49 >

SoC LusSy PINAPA BISE Conclusion

The LUSSY Tool Chain

Transformations Abstract Format (in memory) Concrete Format (file) External tools/formats SystemC Abstract SystemC Pinapa Bise Verification tool tool-specific format Property

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 24 / 49 >

SoC LusSy PINAPA BISE Conclusion

The LUSSY Tool Chain

Transformations Abstract Format (in memory) Concrete Format (file) External tools/formats SystemC Abstract SystemC HPIOM Pinapa Bise Verification tool tool-specific format Property

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 24 / 49 >

SoC LusSy PINAPA BISE Conclusion

The LUSSY Tool Chain

Transformations Abstract Format (in memory) Concrete Format (file) External tools/formats SystemC Abstract SystemC HPIOM Pinapa Bise Back-end Verification tool tool-specific format Property

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 24 / 49 >

SoC LusSy PINAPA BISE Conclusion

The LUSSY Tool Chain

Transformations Abstract Format (in memory) Concrete Format (file) External tools/formats SystemC Abstract SystemC HPIOM Pinapa Bise Birth Back-end Verification tool tool-specific format Property

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 24 / 49 >

SoC LusSy PINAPA BISE Conclusion

The LUSSY Tool Chain

Transformations Abstract Format (in memory) Concrete Format (file) External tools/formats SystemC Abstract SystemC HPIOM Pinapa Bise Birth Back-end Verification tool tool-specific format Property

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 24 / 49 >

SoC LusSy PINAPA BISE Conclusion

The LUSSY Tool Chain

Transformations Abstract Format (in memory) Concrete Format (file) External tools/formats SystemC Abstract SystemC HPIOM Pinapa Bise Birth Back-end Verification tool tool-specific format Property Lustre SMV

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 24 / 49 >

SoC LusSy PINAPA BISE Conclusion

The LUSSY Tool Chain

Transformations Abstract Format (in memory) Concrete Format (file) External tools/formats SystemC Abstract SystemC HPIOM Pinapa Bise Birth Back-end Verification tool tool-specific format Property Lustre SMV Lesar SMV nbac gbac Prover

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 24 / 49 >

SoC LusSy PINAPA BISE Conclusion

The LUSSY Tool Chain

Transformations Abstract Format (in memory) Concrete Format (file) External tools/formats SystemC Abstract SystemC HPIOM Pinapa Bise Birth Back-end Verification tool tool-specific format Property Lustre SMV Lesar SMV nbac gbac Prover ??? ???

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 24 / 49 >

SoC LusSy PINAPA BISE Conclusion

The LUSSY Tool Chain

Transformations Abstract Format (in memory) Concrete Format (file) External tools/formats SystemC Abstract SystemC HPIOM Pinapa Bise Birth Back-end Verification tool tool-specific format Property Lustre SMV Lesar SMV nbac gbac Prover ??? ???

LusSy

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 24 / 49 >

SoC LusSy PINAPA BISE Conclusion

Outline

1

Context: Embedded Systems and Systems-on-a-Chip

2

LUSSY: A Toolbox for the Analysis of Systems-on-a-Chip at the Transaction Level

3

PINAPA: Syntax and Architecture Extraction

4

BISE: Semantic Extraction

5

Conclusion

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 25 / 49 >

SoC LusSy PINAPA BISE Conclusion

PINAPA: Pinapa Is Not A PArser

SystemC Abstract SystemC HPIOM Pinapa Bise Birth Back-end Verification tool tool-specific format Property

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 26 / 49 >

SoC LusSy PINAPA BISE Conclusion

Main Choices

There are many ways to “parse” SystemC: Write a grammar from scratch ⇒ Needs to take all the C++ grammar into account!

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 27 / 49 >

SoC LusSy PINAPA BISE Conclusion

Main Choices

There are many ways to “parse” SystemC: Write a grammar from scratch ⇒ Needs to take all the C++ grammar into account! Use a C++ front-end, and nothing else ⇒ Misses important information like architecture, built at run-time

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 27 / 49 >

SoC LusSy PINAPA BISE Conclusion

Main Choices

There are many ways to “parse” SystemC: Write a grammar from scratch ⇒ Needs to take all the C++ grammar into account! Use a C++ front-end, and nothing else ⇒ Misses important information like architecture, built at run-time Use a C++ front-end, and recognize patterns in the elaboration phase ⇒ Big limitation on the coding style of the elaboration

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 27 / 49 >

SoC LusSy PINAPA BISE Conclusion

Main Choices

There are many ways to “parse” SystemC: Write a grammar from scratch ⇒ Needs to take all the C++ grammar into account! Use a C++ front-end, and nothing else ⇒ Misses important information like architecture, built at run-time Use a C++ front-end, and recognize patterns in the elaboration phase ⇒ Big limitation on the coding style of the elaboration Use a C++ front-end, and execute the elaboration phase to get the architecture ⇒ Much less limitation, lot of code reuse

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 27 / 49 >

SoC LusSy PINAPA BISE Conclusion

Main Choices

There are many ways to “parse” SystemC: Write a grammar from scratch ⇒ Needs to take all the C++ grammar into account! ParSyC, SystemPerl, sc2v, KaSCPar Use a C++ front-end, and nothing else ⇒ Misses important information like architecture, built at run-time Use a C++ front-end, and recognize patterns in the elaboration phase ⇒ Big limitation on the coding style of the elaboration SystemCXML, CoCentric Use a C++ front-end, and execute the elaboration phase to get the architecture ⇒ Much less limitation, lot of code reuse Approach chosen for PINAPA

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 27 / 49 >

SoC LusSy PINAPA BISE Conclusion

Static Vs Dynamic Information in SystemC Programs

Static Dynamic Pinapa C++ compiler Information in SystemC

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 28 / 49 >

SoC LusSy PINAPA BISE Conclusion

Static Vs Dynamic Information in SystemC Programs

Static Dynamic Pinapa C++ compiler Information in SystemC Behavior Architecture Syntax Lexicography

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 28 / 49 >

SoC LusSy PINAPA BISE Conclusion

Static Vs Dynamic Information in SystemC Programs

Static Dynamic Pinapa C++ compiler Information in SystemC Behavior Architecture Syntax Lexicography Simulation Elaboration Execution Tree (AST) Abstract Syntax

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 28 / 49 >

SoC LusSy PINAPA BISE Conclusion

Static Vs Dynamic Information in SystemC Programs

Static Dynamic Pinapa C++ compiler Information in SystemC Behavior Architecture Syntax Lexicography Simulation Elaboration Execution Tree (AST) Abstract Syntax

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 28 / 49 >

SoC LusSy PINAPA BISE Conclusion

Static Vs Dynamic Information in SystemC Programs

Static Dynamic Pinapa C++ compiler Information in SystemC Behavior Architecture Syntax Lexicography Simulation Elaboration Execution Tree (AST) Abstract Syntax Simulation + AST ELAB

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 28 / 49 >

SoC LusSy PINAPA BISE Conclusion

Static Vs Dynamic Information in SystemC Programs

Static Dynamic Pinapa C++ compiler Information in SystemC Behavior Architecture Syntax Lexicography Simulation Elaboration Execution Tree (AST) Abstract Syntax Simulation + AST ELAB Output of Pinapa

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 28 / 49 >

SoC LusSy PINAPA BISE Conclusion

PINAPA: Key Ideas

Syntax extraction (AST)

◮ Easy if you have a C++ parser ◮ ⇒ Let’s reuse GCC

Architecture extraction (ELAB)

◮ Architecture is built at run-time ◮ ⇒ Let’s execute the elaboration of the program Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 29 / 49 >

SoC LusSy PINAPA BISE Conclusion

PINAPA: Key Ideas

Syntax extraction (AST)

◮ Easy if you have a C++ parser ◮ ⇒ Let’s reuse GCC

Architecture extraction (ELAB)

◮ Architecture is built at run-time ◮ ⇒ Let’s execute the elaboration of the program

Then, what’s difficult??

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 29 / 49 >

SoC LusSy PINAPA BISE Conclusion

PINAPA: Key Ideas

Syntax extraction (AST)

◮ Easy if you have a C++ parser ◮ ⇒ Let’s reuse GCC

Architecture extraction (ELAB)

◮ Architecture is built at run-time ◮ ⇒ Let’s execute the elaboration of the program

We have to link the syntax and architecture information

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 29 / 49 >

SoC LusSy PINAPA BISE Conclusion

Link Between ELAB and AST

ELAB

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 30 / 49 >

SoC LusSy PINAPA BISE Conclusion

Link Between ELAB and AST

ELAB AST

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 30 / 49 >

SoC LusSy PINAPA BISE Conclusion

Link Between ELAB and AST

ELAB AST

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 30 / 49 >

SoC LusSy PINAPA BISE Conclusion

Link Between ELAB and AST

ELAB AST

p.read() port.write(val) Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 30 / 49 >

SoC LusSy PINAPA BISE Conclusion

Link Between ELAB and AST: an Example

port.write(val);

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 31 / 49 >

SoC LusSy PINAPA BISE Conclusion

Link Between ELAB and AST: an Example

port.write(val);

write val port

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 31 / 49 >

SoC LusSy PINAPA BISE Conclusion

Link Between ELAB and AST: an Example

port.write(val);

write val port

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 31 / 49 >

SoC LusSy PINAPA BISE Conclusion

Link Between ELAB and AST: an Example

port.write(val);

write val port

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 31 / 49 >

SoC LusSy PINAPA BISE Conclusion

Link Between ELAB and AST: an Example

port.write(val);

write val port

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 31 / 49 >

SoC LusSy PINAPA BISE Conclusion

PINAPA: steps of execution

SystemC program

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 32 / 49 >

SoC LusSy PINAPA BISE Conclusion

PINAPA: steps of execution

SystemC program Compilation Executable

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 32 / 49 >

SoC LusSy PINAPA BISE Conclusion

PINAPA: steps of execution

SystemC program Compilation Executable Execution ELAB

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 32 / 49 >

SoC LusSy PINAPA BISE Conclusion

PINAPA: steps of execution

SystemC program Compilation Executable Execution ELAB C++ parser AST

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 32 / 49 >

SoC LusSy PINAPA BISE Conclusion

PINAPA: steps of execution

SystemC program Compilation Executable Execution ELAB C++ parser AST Link AST+ELAB

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 32 / 49 >

SoC LusSy PINAPA BISE Conclusion

PINAPA: steps of execution

SystemC program Compilation Executable Execution ELAB C++ parser AST Link AST+ELAB Back-end

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 32 / 49 >

SoC LusSy PINAPA BISE Conclusion

Limitations of the Approach

No limitation regarding the code of the elaboration

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 33 / 49 >

SoC LusSy PINAPA BISE Conclusion

Limitations of the Approach

No limitation regarding the code of the elaboration AST and ELAB built correctly in any case, only link may be problematic.

◮ Dynamic objects (pointers, reference) can hardly be specified with

static information

◮ Templates makes the task harder Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 33 / 49 >

SoC LusSy PINAPA BISE Conclusion

Limitations of the Approach

No limitation regarding the code of the elaboration AST and ELAB built correctly in any case, only link may be problematic.

◮ Dynamic objects (pointers, reference) can hardly be specified with

static information

◮ Templates makes the task harder

Much less limitations than other tools

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 33 / 49 >

SoC LusSy PINAPA BISE Conclusion

Conclusion about PINAPA

Our approach allowed us to write a SystemC front-end

◮ With very few limitations ◮ Managing the TAC and BASIC channels ◮ With a minimal effort (< 4000 lines of C++) Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 34 / 49 >

SoC LusSy PINAPA BISE Conclusion

Conclusion about PINAPA

Our approach allowed us to write a SystemC front-end

◮ With very few limitations ◮ Managing the TAC and BASIC channels ◮ With a minimal effort (< 4000 lines of C++)

PINAPA is Open Source! ⇒ http://greensocs.sourceforge.net/pinapa/

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 34 / 49 >

SoC LusSy PINAPA BISE Conclusion

Outline

1

Context: Embedded Systems and Systems-on-a-Chip

2

LUSSY: A Toolbox for the Analysis of Systems-on-a-Chip at the Transaction Level

3

PINAPA: Syntax and Architecture Extraction

4

BISE: Semantic Extraction

5

Conclusion

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 35 / 49 >

SoC LusSy PINAPA BISE Conclusion

BISE: Back-end Independent Semantics Extraction

SystemC Abstract SystemC HPIOM Pinapa Bise Birth Back-end Verification tool tool-specific format Property

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 36 / 49 >

SoC LusSy PINAPA BISE Conclusion

HPIOM: Heterogeneous Parallel Input/Output

Machines

A formalism of communicating automata With both explicit states and variables Using a synchronous product

!s y := x + 2 [x ≥ y] [x < y] x := 0 s ?s

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 37 / 49 >

SoC LusSy PINAPA BISE Conclusion

Semantics of SystemC in terms of automata

Generate a set of automata including:

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 38 / 49 >

SoC LusSy PINAPA BISE Conclusion

Semantics of SystemC in terms of automata

Generate a set of automata including: One automaton per process (the control flow)

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 38 / 49 >

SoC LusSy PINAPA BISE Conclusion

Semantics of SystemC in terms of automata

Generate a set of automata including: One automaton per process (the control flow) Plus SystemC objects

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 38 / 49 >

SoC LusSy PINAPA BISE Conclusion

Semantics of SystemC in terms of automata

Generate a set of automata including: One automaton per process (the control flow) Plus SystemC objects And the scheduler

Scheduler

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 38 / 49 >

SoC LusSy PINAPA BISE Conclusion

Semantics of SystemC in terms of automata

Generate a set of automata including: One automaton per process (the control flow) Plus SystemC objects And the scheduler

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 38 / 49 >

SoC LusSy PINAPA BISE Conclusion

Direct Semantics Vs Translation

Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 39 / 49 >

SoC LusSy PINAPA BISE Conclusion

Direct Semantics Vs Translation

Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton

Scheduler

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 39 / 49 >

SoC LusSy PINAPA BISE Conclusion

Direct Semantics Vs Translation

Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton

Scheduler User code: Automatic translation

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 39 / 49 >

SoC LusSy PINAPA BISE Conclusion

Direct Semantics Vs Translation

Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton

Scheduler User code: Automatic translation SystemC kernel: Direct semantics

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 39 / 49 >

SoC LusSy PINAPA BISE Conclusion

Direct Semantics Vs Translation

Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton

Scheduler User code: Automatic translation SystemC kernel: Direct semantics Direct semantics Communication:

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 39 / 49 >

SoC LusSy PINAPA BISE Conclusion

Translating C++ code into HPIOM

Nothing new, but has to be done . . . x = x + 1; x := x + 1

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 40 / 49 >

SoC LusSy PINAPA BISE Conclusion

Translating C++ code into HPIOM

Nothing new, but has to be done . . . x = x + 1; y = x + 2; x := x + 1 y := x + 2

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 40 / 49 >

SoC LusSy PINAPA BISE Conclusion

Translating C++ code into HPIOM

Nothing new, but has to be done . . . while (x <= 3) { x = x + 1; y = x + 2; } x := x + 1 y := x + 2 [x ≥ 3] [x < 3]

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 40 / 49 >

SoC LusSy PINAPA BISE Conclusion

The SystemC scheduler

Non-preemptive scheduler

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 41 / 49 >

SoC LusSy PINAPA BISE Conclusion

The SystemC scheduler

Non-preemptive scheduler Non-deterministic processes election

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 41 / 49 >

SoC LusSy PINAPA BISE Conclusion

The SystemC scheduler

Non-preemptive scheduler Non-deterministic processes election Init

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 41 / 49 >

SoC LusSy PINAPA BISE Conclusion

The SystemC scheduler

Non-preemptive scheduler Non-deterministic processes election Init Select process Run

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 41 / 49 >

SoC LusSy PINAPA BISE Conclusion

The SystemC scheduler

Non-preemptive scheduler Non-deterministic processes election Init Select process Run

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 41 / 49 >

SoC LusSy PINAPA BISE Conclusion

The SystemC scheduler

Non-preemptive scheduler Non-deterministic processes election Init Select process Run Update

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 41 / 49 >

SoC LusSy PINAPA BISE Conclusion

The SystemC scheduler

Non-preemptive scheduler Non-deterministic processes election Init Select process Run Update Time elapse

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 41 / 49 >

SoC LusSy PINAPA BISE Conclusion

The SystemC scheduler

Non-preemptive scheduler Non-deterministic processes election Init Select process Run Update Time elapse

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 41 / 49 >

SoC LusSy PINAPA BISE Conclusion

State of a process in the SystemC scheduler

Election of a process is done in two phases:

1

Make the process eligible

2

Run it

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 42 / 49 >

SoC LusSy PINAPA BISE Conclusion

State of a process in the SystemC scheduler

Election of a process is done in two phases:

1

Make the process eligible

2

Run it

For each process, create an automaton representing its state in the scheduler (∈ (eligible, run, sleep)).

. .

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 42 / 49 >

SoC LusSy PINAPA BISE Conclusion

State of a process in the SystemC scheduler

Election of a process is done in two phases:

1

Make the process eligible

2

Run it

For each process, create an automaton representing its state in the scheduler (∈ (eligible, run, sleep)).

. .

Eligible

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 42 / 49 >

SoC LusSy PINAPA BISE Conclusion

State of a process in the SystemC scheduler

Election of a process is done in two phases:

1

Make the process eligible

2

Run it

For each process, create an automaton representing its state in the scheduler (∈ (eligible, run, sleep)).

. .

Eligible Run ?elect

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 42 / 49 >

SoC LusSy PINAPA BISE Conclusion

State of a process in the SystemC scheduler

Election of a process is done in two phases:

1

Make the process eligible

2

Run it

For each process, create an automaton representing its state in the scheduler (∈ (eligible, run, sleep)).

. .

Eligible Run ?elect Sleep ?wait(e)

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 42 / 49 >

SoC LusSy PINAPA BISE Conclusion

State of a process in the SystemC scheduler

Election of a process is done in two phases:

1

Make the process eligible

2

Run it

For each process, create an automaton representing its state in the scheduler (∈ (eligible, run, sleep)).

. .

Eligible Run ?elect Sleep ?wait(e) ?notify(e)

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 42 / 49 >

SoC LusSy PINAPA BISE Conclusion

State of a process in the SystemC scheduler

Election of a process is done in two phases:

1

Make the process eligible

2

Run it

For each process, create an automaton representing its state in the scheduler (∈ (eligible, run, sleep)).

. .

Eligible Run ?elect Sleep ?wait(e) ?notify(e) Sleep’ ?wait(e′) ?notify(e′)

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 42 / 49 >

SoC LusSy PINAPA BISE Conclusion

State of a process in the SystemC scheduler

Election of a process is done in two phases:

1

Make the process eligible

2

Run it

For each process, create an automaton representing its state in the scheduler (∈ (eligible, run, sleep)).

. .

Eligible Run ?elect Sleep ?wait(e) ?notify(e) Sleep’ ?wait(e′) ?notify(e′)

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 42 / 49 >

SoC LusSy PINAPA BISE Conclusion

Semantics of SystemC Boolean Signals

SystemC sc_signal avoids scheduling dependencies:

1

read takes the current value, but

2

write will be taken into account at the next update phase.

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 43 / 49 >

SoC LusSy PINAPA BISE Conclusion

Semantics of SystemC Boolean Signals

SystemC sc_signal avoids scheduling dependencies:

1

read takes the current value, but

2

write will be taken into account at the next update phase.

Current value True False

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 43 / 49 >

SoC LusSy PINAPA BISE Conclusion

Semantics of SystemC Boolean Signals

SystemC sc_signal avoids scheduling dependencies:

1

read takes the current value, but

2

write will be taken into account at the next update phase.

Next value True False Current value True False

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 43 / 49 >

SoC LusSy PINAPA BISE Conclusion

Semantics of SystemC Boolean Signals

SystemC sc_signal avoids scheduling dependencies:

1

read takes the current value, but

2

write will be taken into account at the next update phase.

Next value True False Current value True False

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 43 / 49 >

SoC LusSy PINAPA BISE Conclusion

Semantics of SystemC Boolean Signals

SystemC sc_signal avoids scheduling dependencies:

1

read takes the current value, but

2

write will be taken into account at the next update phase.

Next value True False Current value True False

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 43 / 49 >

SoC LusSy PINAPA BISE Conclusion

Semantics of SystemC Boolean Signals

SystemC sc_signal avoids scheduling dependencies:

1

read takes the current value, but

2

write will be taken into account at the next update phase.

Next value True False Current value True False ?write(F)

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 43 / 49 >

SoC LusSy PINAPA BISE Conclusion

Semantics of SystemC Boolean Signals

SystemC sc_signal avoids scheduling dependencies:

1

read takes the current value, but

2

write will be taken into account at the next update phase.

Next value True False Current value True False ?write(F) ?write(T)

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 43 / 49 >

SoC LusSy PINAPA BISE Conclusion

Semantics of SystemC Boolean Signals

SystemC sc_signal avoids scheduling dependencies:

1

read takes the current value, but

2

write will be taken into account at the next update phase.

Next value True False Current value True False ?write(F) ?write(T) ?write(T) ?write(F)

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 43 / 49 >

SoC LusSy PINAPA BISE Conclusion

Semantics of SystemC Boolean Signals

SystemC sc_signal avoids scheduling dependencies:

1

read takes the current value, but

2

write will be taken into account at the next update phase.

Next value True False Current value True False ?write(F) ?write(T) ?write(T) ?write(F) ?update ?update

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 43 / 49 >

SoC LusSy PINAPA BISE Conclusion

Semantics of SystemC Boolean Signals

SystemC sc_signal avoids scheduling dependencies:

1

read takes the current value, but

2

write will be taken into account at the next update phase.

Next value True False Current value True False ?write(F) ?write(T) ?write(T) ?write(F) ?update ?update !event !event

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 43 / 49 >

SoC LusSy PINAPA BISE Conclusion

Semantics of SystemC Boolean Signals

SystemC sc_signal avoids scheduling dependencies:

1

read takes the current value, but

2

write will be taken into account at the next update phase.

Next value True False Current value True False ?write(F) ?write(T) ?write(T) ?write(F) ?update ?update !event !event

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 43 / 49 >

SoC LusSy PINAPA BISE Conclusion

Direct Semantics Vs Translation

Translation = Parse the source code, generate an automaton Direct semantics = Read the specification, instantiate an automaton

Scheduler User code: Automatic translation SystemC kernel: Direct semantics Direct semantics Communication:

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 44 / 49 >

SoC LusSy PINAPA BISE Conclusion

Outline

1

Context: Embedded Systems and Systems-on-a-Chip

2

LUSSY: A Toolbox for the Analysis of Systems-on-a-Chip at the Transaction Level

3

PINAPA: Syntax and Architecture Extraction

4

BISE: Semantic Extraction

5

Conclusion

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 45 / 49 >

SoC LusSy PINAPA BISE Conclusion

Other components not detailed here

BIRTH : HPIOM to HPIOM transformations (Back-end Independent Reduction and Transformation of Hpiom)

SystemC Abstract SystemC HPIOM Pinapa Bise Birth Back-end Verification tool tool-specific format Property

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 46 / 49 >

SoC LusSy PINAPA BISE Conclusion

Other components not detailed here

BIRTH : HPIOM to HPIOM transformations (Back-end Independent Reduction and Transformation of Hpiom) Back-ends: Connection to verification tools

SystemC Abstract SystemC HPIOM Pinapa Bise Birth Back-end Verification tool tool-specific format Property

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 46 / 49 >

SoC LusSy PINAPA BISE Conclusion

Results

The complete LUSSY tool-chain is operational From SystemC program to “yes/no+diagnosis” Methodology to debug and validate LUSSY itself Accurate modeling of SystemC semantics

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 47 / 49 >

SoC LusSy PINAPA BISE Conclusion

Results

The complete LUSSY tool-chain is operational From SystemC program to “yes/no+diagnosis” Methodology to debug and validate LUSSY itself Accurate modeling of SystemC semantics Results of the verification tools

◮ Able to find well hidden bugs in small programs Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 47 / 49 >

SoC LusSy PINAPA BISE Conclusion

Results

The complete LUSSY tool-chain is operational From SystemC program to “yes/no+diagnosis/state explosion” Methodology to debug and validate LUSSY itself Accurate modeling of SystemC semantics Results of the verification tools

◮ Able to find well hidden bugs in small programs ◮ But state explosion on medium and large programs Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 47 / 49 >

SoC LusSy PINAPA BISE Conclusion

Results

The complete LUSSY tool-chain is operational From SystemC program to “yes/no+diagnosis/state explosion” Methodology to debug and validate LUSSY itself Accurate modeling of SystemC semantics Results of the verification tools

◮ Able to find well hidden bugs in small programs ◮ But state explosion on medium and large programs

So, is this work useless in practice?

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 47 / 49 >

SoC LusSy PINAPA BISE Conclusion

Results

The complete LUSSY tool-chain is operational From SystemC program to “yes/no+diagnosis/state explosion” Methodology to debug and validate LUSSY itself Accurate modeling of SystemC semantics Results of the verification tools

◮ Able to find well hidden bugs in small programs ◮ But state explosion on medium and large programs

LUSSY provides the building blocks, but a lot is still to be done . . .

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 47 / 49 >

SoC LusSy PINAPA BISE Conclusion

Perspectives

Better formal verification

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 48 / 49 >

SoC LusSy PINAPA BISE Conclusion

Perspectives

Better formal verification

◮ Extensive use of abstract interpretation

⇒ Mathias Peron, Ph.D at Verimag

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 48 / 49 >

SoC LusSy PINAPA BISE Conclusion

Perspectives

Better formal verification

◮ Extensive use of abstract interpretation

⇒ Mathias Peron, Ph.D at Verimag

◮ Compositional verification

⇒ Experiments with PROMETHEUS (Yvan Roux, INRIA) ⇒ Towards a joint project with Edmund M. Clarke (CMU)

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 48 / 49 >

SoC LusSy PINAPA BISE Conclusion

Perspectives

Better formal verification

◮ Extensive use of abstract interpretation

⇒ Mathias Peron, Ph.D at Verimag

◮ Compositional verification

⇒ Experiments with PROMETHEUS (Yvan Roux, INRIA) ⇒ Towards a joint project with Edmund M. Clarke (CMU)

Run-time verification: Improve test coverage with a minimal test-bench (will use PINAPA for instrumentation) ⇒ Claude Helmstetter, Ph.D at Verimag/STMicroelectronics ⇒ Yussef Bouzouzou, DRT at Verimag/Silicomp

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 48 / 49 >

SoC LusSy PINAPA BISE Conclusion

Perspectives

Better formal verification

◮ Extensive use of abstract interpretation

⇒ Mathias Peron, Ph.D at Verimag

◮ Compositional verification

⇒ Experiments with PROMETHEUS (Yvan Roux, INRIA) ⇒ Towards a joint project with Edmund M. Clarke (CMU)

Run-time verification: Improve test coverage with a minimal test-bench (will use PINAPA for instrumentation) ⇒ Claude Helmstetter, Ph.D at Verimag/STMicroelectronics ⇒ Yussef Bouzouzou, DRT at Verimag/Silicomp Other tools based on the LUSSY tool-chain

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 48 / 49 >

SoC LusSy PINAPA BISE Conclusion

Perspectives

Better formal verification

◮ Extensive use of abstract interpretation

⇒ Mathias Peron, Ph.D at Verimag

◮ Compositional verification

⇒ Experiments with PROMETHEUS (Yvan Roux, INRIA) ⇒ Towards a joint project with Edmund M. Clarke (CMU)

Run-time verification: Improve test coverage with a minimal test-bench (will use PINAPA for instrumentation) ⇒ Claude Helmstetter, Ph.D at Verimag/STMicroelectronics ⇒ Yussef Bouzouzou, DRT at Verimag/Silicomp Other tools based on the LUSSY tool-chain

◮ SPINAPA: A prototype of SPIRIT back-end for PINAPA developed in

STMicroelectronics (allows for graphical visualization in particular) ⇒ Frédéric Saunier, Silicomp/STMicroelectronics

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 48 / 49 >

SoC LusSy PINAPA BISE Conclusion

Perspectives

Better formal verification

◮ Extensive use of abstract interpretation

⇒ Mathias Peron, Ph.D at Verimag

◮ Compositional verification

⇒ Experiments with PROMETHEUS (Yvan Roux, INRIA) ⇒ Towards a joint project with Edmund M. Clarke (CMU)

Run-time verification: Improve test coverage with a minimal test-bench (will use PINAPA for instrumentation) ⇒ Claude Helmstetter, Ph.D at Verimag/STMicroelectronics ⇒ Yussef Bouzouzou, DRT at Verimag/Silicomp Other tools based on the LUSSY tool-chain

◮ SPINAPA: A prototype of SPIRIT back-end for PINAPA developed in

STMicroelectronics (allows for graphical visualization in particular) ⇒ Frédéric Saunier, Silicomp/STMicroelectronics

◮ Several PINAPA back-ends outside ST/Verimag Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 48 / 49 >

SoC LusSy PINAPA BISE Conclusion

Perspectives

Better formal verification

◮ Extensive use of abstract interpretation

⇒ Mathias Peron, Ph.D at Verimag

◮ Compositional verification

⇒ Experiments with PROMETHEUS (Yvan Roux, INRIA) ⇒ Towards a joint project with Edmund M. Clarke (CMU)

Run-time verification: Improve test coverage with a minimal test-bench (will use PINAPA for instrumentation) ⇒ Claude Helmstetter, Ph.D at Verimag/STMicroelectronics ⇒ Yussef Bouzouzou, DRT at Verimag/Silicomp Other tools based on the LUSSY tool-chain

◮ SPINAPA: A prototype of SPIRIT back-end for PINAPA developed in

STMicroelectronics (allows for graphical visualization in particular) ⇒ Frédéric Saunier, Silicomp/STMicroelectronics

◮ Several PINAPA back-ends outside ST/Verimag ◮ OpenTLM: A Minalogic project including STMicroelectronics,

Verimag, Silicomp-AQL and others

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 48 / 49 >

SoC LusSy PINAPA BISE Conclusion

Questions?

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 49 / 49 >

SoC LusSy PINAPA BISE Conclusion

Backup slides

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 49 / 49 >

SoC LusSy PINAPA BISE Conclusion

Users of PINAPA

SPINAPA: SPIRIT back-end (Frédéric Saunier, STMicroelectronics/Silicomp) Theorem proving (Primrose Mbanefo) Platform Based Design Methodology (Humberto Rocha) Introspection in SystemC (Diogo Alves) Connection to PROMETHEUS (Yvan Roux, INRIA) 9 other subscribers on the mailing list.

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 49 / 49 >

SoC LusSy PINAPA BISE Conclusion

PINAPA and dynamic objects

No management of pointers/references to SystemC objects port_array[42] managed exactly as a normal port (because 42 is a constant) port_array[x + y]: PINAPA attaches a pointer to port_array[0] and the AST for “x + y”

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 49 / 49 >

SoC LusSy PINAPA BISE Conclusion

Examples of Properties on a TLM

int x = 42; int addr = 8; tlm_status status; while (true) {

• ut_bool.write(false);

status=p.write(addr, &x); } (in_bool.read() == false); ASSERT if(*source == 4322) { set_access_error(); } int x = 4321; int address = 0; while (true) { } tlm_status s; s = port.write(address, &x); ASSERT(!s.is_no_response()); ASSERT(!s.is_error());

Matthieu Moy (Verimag/STMicroelectronics) Ph.D presentation December 9th, 2005 < 49 / 49 >