Génération de tests basés sur les modèles pour des systèmes sur puce avec cohérence de caches Massimo Zendri & Abderahman Kriouile STMicroelectronics DCG / IP dev / FVS
Model based test generation for cache coherent Systems On Chips Massimo Zendri & Abderahman Kriouile STMicroelectronics DCG / IP dev / FVS
Where you find us 3 Our MEMS & Sensors Our digital consumer products are augmenting are powering the augmented the consumer experience digital lifestyle Our automotive products Our Microcontrollers are making driving safer, are everywhere greener and more making everything smarter entertaining and more secure Our smart power products are allowing our mobile products to operate longer and making more of our energy resources
Towards the Home Cloud 4 Medium Screen Clients Small Screen Clients Home Automation Home Cloud Clients Broadcast Set-Top Box Personal Big Screens Over-The-Top Clients On the Move Services Operator Managed Home gateway Network & Services Connected Client & Server
Heterogeneous System-on-Chip (SoC) 5 Need for System-Level Cache Coherency ARM proposed ACE specification: standard for system level cache coherency
Simulation-Based Testing 6 Abstract Abstract Abstract CPU CPU video with with decoder cache cache without cache Cache Coherent Interconnect (CCI) Verilog/VHDL A. KRIOUILE, W. SERWE Using Formal Model to Improve Verification of Cache-Coherent SoC
Simulation-Based Testing 7 Interface-level Abstract Abstract Abstract CPU CPU video with with decoder • Assertions: CPU behavior cache cache without • Constraints: CCI behavior cache Expressed as SystemVerilog assertions or PSL properties Monitor Monitor Monitor Cache Coherent Interconnect (CCI) Verilog/VHDL Formal blocks Non-formal blocks A. KRIOUILE, W. SERWE Using Formal Model to Improve Verification of Cache-Coherent SoC
Model Checking 8 (without running any test) Assertions (CCI || Constraints ) ╞ Assertion i Monitor Monitor Monitor Constraints Cache Coherent Interconnect (CCI) Verilog/VHDL • Applying restrictions for more exploration • Limitation due to state-space explosion problem
HW Model Based Test Generator 9
Need for System-Level Verification 10 System-level Abstract Abstract Abstract CPU CPU GPU with with without cache cache cache Monitor Monitor Monitor W (L, D 1 ) W (L, D 2 ) Cache Coherent Interconnect (CCI) Verilog/VHDL W (L, D 1 ) W (L, D 1 ) W (L, D 2 )
Formal Model of an ACE-based SoC 11 ACE master 1 (big) ACE master 2 (LITTLE) ACE-Lite master (GPU) Line_1 Line_2 Line_1 Line_2 W B AR R AW W B AC CR CD AR R AW W B AC CR CD AR R AW ACE port 1 ACE port 2 ACE-Lite port CCI AXI port (cache-coherent interconnect) AR R AW W B AXI slave (non-cache-coherent NoC/memory) • Interface transfers modeled by rendezvous • 3400 lines of LNT code derived from ACE specification • Parametric: #masters, forbidden ACE transactions, … • [Kriouile-Serwe-13] Formal Analysis of the ACE Specification for Cache Coherent Systems-on-Chip , FMICS, LNCS 8187, 2013
CADP: OCIS ( Open/Cæsar Interactive Simulator ) 12 • language-independent • tree-like scenarios • save/load scenarios • source code access • dynamic recompile
Generation of System-Level Test Cases 13 function CIC interesting formal restricted configurations model model system model checker test generation properties abstract [Tretmans-92] test cases counter- [ Jard-Jeron-05] examples IVK coverage-directed test solver purposes concrete RTL tests
IVK (Interconnect Verification Kit): 14 Automated Interconnect Testbench Generation Framework setup design HDL wrapping AXI AXI AXI T3 Active Active Active Active Master agent Master agent Master agent Initiator agent DUT ICN Interconnect Scoreboard ICN TDL T3 AXI AHB APB T1 Active Active Active Active Active Target agent Slave agent Slave agent Slave agent Target agent tests checks coverage Inputs Outputs Architectural description (TDL) either Full Verification Environment, generated by interconnect designers including sequences and coverage GUI or through Excel flow models
Several Kinds of Derived Tests 15 •39 + 3 generated CTGs (Complete Test Graphs) > •296 simple system-level tests • for each correct initial state with two masters possibly sharing a memory line, initiate all permitted transitions • check correct behavior of the Cache Coherent Interconnect (e.g., generation of corresponding snoops) •10 sequence tests to recreate counter-examples • concurrency between transactions • conditioned by response of the Cache Coherent Interconnect
Results 16 • 300 IVK tests generated • Many problems identified on the verification environment (VIP components) • System level assertions to check system behavior • 100% coverage of system level assertions • Reproduction of 1 suspected architectural issue • Used on 2 currently developed products (codenamed Orly3 and Barcelona)
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