Gnration de tests bass sur les modles pour des systmes sur puce - - PowerPoint PPT Presentation

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Gnration de tests bass sur les modles pour des systmes sur puce - - PowerPoint PPT Presentation

Jan 15, 2023 272 likes •437 views

Gnration de tests bass sur les modles pour des systmes sur puce avec cohrence de caches Massimo Zendri & Abderahman Kriouile STMicroelectronics DCG / IP dev / FVS Model based test generation for cache coherent Systems On Chips

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SLIDE 1

Génération de tests basés sur les modèles pour des systèmes sur puce avec cohérence de caches

Massimo Zendri & Abderahman Kriouile STMicroelectronics DCG / IP dev / FVS

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SLIDE 2

Model based test generation for cache coherent Systems On Chips

Massimo Zendri & Abderahman Kriouile STMicroelectronics DCG / IP dev / FVS

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SLIDE 3

Where you find us

3 Our automotive products are making driving safer, greener and more entertaining Our smart power products are allowing our mobile products to operate longer and making more of our energy resources Our MEMS & Sensors are augmenting the consumer experience Our Microcontrollers are everywhere making everything smarter and more secure Our digital consumer products are powering the augmented digital lifestyle

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SLIDE 4

Towards the Home Cloud

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Personal Clients

Over-The-Top Services Operator Managed Network & Services

Home Automation Clients Small Screen Clients Medium Screen Clients On the Move

Broadcast Set-Top Box

Big Screens

Connected Client & Server Home gateway Home Cloud

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SLIDE 5

Heterogeneous System-on-Chip (SoC)

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Need for System-Level Cache Coherency ARM proposed ACE specification: standard for system level cache coherency

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SLIDE 6

Simulation-Based Testing

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Abstract CPU with cache Abstract CPU with cache Abstract video decoder without cache

Cache Coherent Interconnect (CCI) Verilog/VHDL

Using Formal Model to Improve Verification of Cache-Coherent SoC

  • A. KRIOUILE, W. SERWE
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SLIDE 7

Simulation-Based Testing

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Abstract CPU with cache Abstract CPU with cache Abstract video decoder without cache

Cache Coherent Interconnect (CCI) Verilog/VHDL Monitor Monitor Monitor Interface-level Formal blocks Non-formal blocks

  • Assertions: CPU behavior
  • Constraints: CCI behavior

Expressed as SystemVerilog assertions or PSL properties

Using Formal Model to Improve Verification of Cache-Coherent SoC

  • A. KRIOUILE, W. SERWE
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SLIDE 8

Model Checking

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Monitor Monitor Monitor

Cache Coherent Interconnect (CCI) Verilog/VHDL

Assertions

(CCI || Constraints) ╞ Assertioni

  • Applying restrictions for more exploration
  • Limitation due to state-space explosion problem

(without running any test)

Constraints

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SLIDE 9

HW Model Based Test Generator

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SLIDE 10

Need for System-Level Verification

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Abstract CPU with cache Abstract CPU with cache Abstract GPU without cache

Monitor Monitor W (L, D1) System-level Cache Coherent Interconnect (CCI) Verilog/VHDL Monitor W (L, D1) W (L, D2) W (L, D2) W (L, D1)

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SLIDE 11

Formal Model of an ACE-based SoC

  • Interface transfers modeled by rendezvous
  • 3400 lines of LNT code derived from ACE specification
  • Parametric: #masters, forbidden ACE transactions, …
  • [Kriouile-Serwe-13] Formal Analysis of the ACE Specification for

Cache Coherent Systems-on-Chip, FMICS, LNCS 8187, 2013

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ACE master 1 (big)

Line_1 Line_2

ACE master 2 (LITTLE)

Line_1 Line_2

ACE-Lite master (GPU) CCI

(cache-coherent interconnect) ACE port 1 ACE port 2 ACE-Lite port AXI port

AXI slave (non-cache-coherent NoC/memory)

AR AW R W AC B CD CR AR AW R W AC B CD CR AR AW R W B AR AW R W B

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SLIDE 12

CADP: OCIS (Open/Cæsar Interactive Simulator)

  • language-independent
  • tree-like scenarios
  • save/load scenarios
  • source code access
  • dynamic recompile

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SLIDE 13

IVK

Generation of System-Level Test Cases

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function CIC

system properties formal model interesting configurations test purposes abstract test cases concrete RTL tests coverage-directed solver

test generation

model checker restricted model counter- examples

[Jard-Jeron-05]

[Tretmans-92]

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SLIDE 14

IVK (Interconnect Verification Kit):

Automated Interconnect Testbench Generation

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  • Inputs

Architectural description (TDL) either generated by interconnect designers GUI or through Excel flow

  • Outputs

Full Verification Environment, including sequences and coverage models ICN TDL

AXI Active Slave agent AXI Active Master agent T3 Active Initiator agent T3 Active Target agent Interconnect AXI Active Master agent AXI Active Master agent AHB Active Slave agent APB Active Slave agent T1 Active Target agent ICN Scoreboard

DUT

design

Framework setup

coverage

HDL wrapping

tests checks

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SLIDE 15

Several Kinds of Derived Tests

  • 39 + 3 generated CTGs (Complete Test Graphs)
  • 296 simple system-level tests
  • for each correct initial state with two masters possibly sharing a

memory line, initiate all permitted transitions

  • check correct behavior of the Cache Coherent Interconnect (e.g.,

generation of corresponding snoops)

  • 10 sequence tests to recreate counter-examples
  • concurrency between transactions
  • conditioned by response of the Cache Coherent Interconnect

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>

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SLIDE 16

Results

  • 300 IVK tests generated
  • Many problems identified on the verification environment

(VIP components)

  • System level assertions to check system behavior
  • 100% coverage of system level assertions
  • Reproduction of 1 suspected architectural issue
  • Used on 2 currently developed products

(codenamed Orly3 and Barcelona)

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