Static characteristics - 4 VTC I Dn in = 2.5 in = 0 V V PMOS V - - PowerPoint PPT Presentation

EEL7312 – INE5442 Digital Integrated Circuits 1

Source: Rabaey

Static characteristics - 4

Vin Vout V

DD

• VGSp

+

• VDSp

+

IDp IDn

IDn V

• ut

V

in= 2.5

2 1.5 V

in= 0

0.5 1 NMOS V

in= 0

V

in= 0.5

V

in= 1

V

in= 1.5

V

in= 2

V

in= 2.5

1 1.5 PMOS

VTC

Vout 0.5 1 1.5 2 2.5 NMOS res PMOS off NMOS sat PMOS sat NMOS off PMOS res NMOS sat PMOS res NMOS res PMOS sat

in

0.5 1 1.5 2 2.5 V

EEL7312 – INE5442 Digital Integrated Circuits 2

Source: Rabaey

Static characteristics - 5

Vin Vout V

DD

• VGSp

+

• VDSp

+

IDp IDn

IDn V

• ut

V

in= 2.5

2 1.5 V

in= 0

0.5 1 NMOS V

in= 0

V

in= 0.5

V

in= 1

V

in= 1.5

V

in= 2

V

in= 2.5

1 1.5 PMOS

Short-circuit current

IDD

V in 0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5

EEL7312 – INE5442 Digital Integrated Circuits 3

Source: Weste & Harris

Static characteristics - 6

Vin Vout V

DD

• VGSp

+

• VDSp

+

IDp IDn

Switching threshold - 1

EEL7312 – INE5442 Digital Integrated Circuits 4

Source: Weste & Harris

Static characteristics - 7

1

DS

V λ << ; 1 1

M

Tn Tp DD Dn Dp

r r V r r

V V V I I

+ = → = + + +

Vin Vout V

DD

• VGSp

+

• VDSp

+

IDp IDn

Switching threshold - 2

Experimental determination of VM: short-circuit between input and output

Vin Vout

VM

( ) ( ) ( )

( ) (

) ( )

2 2 2 2

1 2 2 1 2 2

n n n DSn n n p p p DSp DD p p

Dn Tn M Tn GSn Dp Tp M Tp GSp

k W k W V L L k k W W V L L

I V V V V I V V V V V

λ λ ⎞ ⎞ ⎛ ⎛ = + ≅ ⎜ ⎟ ⎜ ⎟ ⎝ ⎝ ⎠ ⎠ ⎞ ⎞ ⎛ ⎛ = + ≅ − ⎜ ⎟ ⎜ ⎟ ⎝ ⎝ ⎠ ⎠

− − − −

Usually

( ) ( )

/ /

p p n n

W L k r k W L =

Example: VDD=2.5 V, VTp=-0.4 V, VTn=0.43 V. What is VM for r= 0.5, 1.0, and 1.5? Answer: VM=0.98, 1.26, and 1.43 V, respectively.

EEL7312 – INE5442 Digital Integrated Circuits 5

Source: Weste & Harris

Static characteristics - 8 Noise margins - 1

Vin Vout V

DD

• VGSp

+

• VDSp

+

IDp IDn

EEL7312 – INE5442 Digital Integrated Circuits 6

Source: Rabaey

Static characteristics - 9

Noise margins - 2

Vin Vout V

DD

• VGSp

+

• VDSp

+

IDp IDn

Approximate calculation of VIL and VIH

VOH VOL Vin V

• ut

VM VIL VIH

For regeneration -g>1, g is the gain in transition region

EEL7312 – INE5442 Digital Integrated Circuits 7

Source: Rabaey

Static characteristics - 10 Scaling the supply voltage

Vin V

• ut

VDD

• VGSp

+

• VDSp

+

IDp IDn

0.05 0.1 0.15 0.2 0.05 0.1 0.15 0.2 Vin (V) Vout (V) 0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5 Vin (V) Vout(V)

Effects of supply voltage reduction:

• Energy dissipation decreases but gate delay increases
• dc characteristic becomes more sensitive to variations in device parameters
• Signal swing reduces making the design more sensitive to external noise

sources that do not scale

EEL7312 – INE5442 Digital Integrated Circuits 8

Impact of Process Variations

0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5

V

in(V)

V

• ut

(V)

“Good” PMOS “Bad” NMOS Good NMOS Bad PMOS Nominal

Source: Rabaey

Static characteristics -11

W k L β ′ =

Notes: 1. k’n≈ 2 to 3 k’p 2. For βn=βp and VTp=-VTn, VM=VDD/2

Source: Uyemura

EEL7312 – INE5442 Digital Integrated Circuits 9

Dynamic operation - 1

M

N

v

I

v O M

P

C V = 5 V

DD

(a) M

N

v = 5 V

I

v (0+) = 5V

O

C (b) 0 V + 5V t vI 0 V + 5V t vO

High-to-low output transition in a CMOS inverter

C: load capacitance + interconnect capacitance + capacitances associated with the inverter transistors

Source: Jaeger

EEL7312 – INE5442 Digital Integrated Circuits 10

Source: Jaeger

Dynamic operation - 2

C: load capacitance + interconnect capacitance + capacitances associated with the inverter transistors

M

N

v

I

v O M

P

C V = 5 V

DD

(a) (b) V = 0 V

I

M

P

v (0+) = 0V

O

C V = 5 V

DD

0 V + 5V t vI 0 V + 5V t vO

Low-to- high output transition in a CMOS inverter

EEL7312 – INE5442 Digital Integrated Circuits 11

Source: Uyemura

Dynamic operation - 3

tPHL tPLH

EEL7312 – INE5442 Digital Integrated Circuits 12

Dynamic operation - 4

/2

• ut

DD PHL

• ut

DD

t V V t t V V = → = = → =

Propagation delay - 1

V

DS(V)

ID(A)

VGS= VDD

VDD VDD/2 VGSn=VDD Vout VDD + VDSn

__

ID IC

• ut

D C

dV C dt

I I

= = −

( )

/ 2 / 2

/2 1 /2

PHL DD DD DD DD

t V

• ut

DD PHL Dav V V Dav D DS DS DD V

D

dV CV dt C t I I I V dV V

I

= − → = =

∫ ∫ ∫

EEL7312 – INE5442 Digital Integrated Circuits 13

Dynamic operation - 5

( ) ( )

2 2

for 2 /2 for

n DS n n DS DS DS n

D Tn Tn GS GS D Tn Tn GS GS

k W V L W k V V V L

I V V V V I V V V V

⎞ ⎛ ≅ > ⎜ ⎟ ⎝ ⎠ ⎞ ⎛ ⎡ ⎤ ≅ − ≤ ⎜ ⎟ ⎣ ⎦ ⎝ ⎠

− − − −

Propagation delay - 2

( )

2

/2 /2 ; 2

DD DD PHL n Dav n PHL n n

D DD D Tn

C C t W V CV t k W I L L k

V V V

≈ ⎞ ⎛ ⎜ ⎟ = ≈ ⎞ ⎛ ⎜ ⎟ ⎝ ⎠ ⎝ ⎠

−

V

DS(V)

ID(A)

VGS= VDD

VDD VDD/2 Let us assume that ( )

2 and that

2

n Dsat DD n

Dav DD Tn Tn

k W I V L

I V V V

⎞ ⎛ ≅ = >> ⎜ ⎟ ⎝ ⎠

−

In this case we have

( )

/ 2

/2 1 /2

DD DD

DD PHL Dav V Dav D DS DS DD V

CV t I I I V dV V = =

∫

V

DD

V

• ut

V

in= VDD

C

Iav

Source: Rabaey

Approach 1 Approach 1

EEL7312 – INE5442 Digital Integrated Circuits 14

Dynamic operation - 6

( )

2 and

2 that

p Dsat DD p

Dav DD Tp Tp

k W I V L

I V V V

⎞ ⎛ ≅ = >> − ⎜ ⎟ ⎝ ⎠

+

Propagation delay - 3

( )

2

/2 /2 ; 2

DD DD PLH p Dav n PLH p p

D DD D Tp

C C t W V CV t k W I L L k

V V V

≈ ⎞ ⎛ ⎜ ⎟ = ≈ ⎞ ⎛ ⎜ ⎟ ⎝ ⎠ ⎝ ⎠

+

Comments:

• kn≈2-3 kp, kn,p=μn,p ·Cox
• Increasing VDD reduces tp but power goes up
• tPLH can be ≈ tPHL by making (W/L)p≈2-3(W/L)n

BUT C is dependent on transistor dimensions

• C includes load (fan-out), wire, inverter “self-

capacitance”

• C is non linear

V

DD

V

• ut

V

in= VDD

C

Iav

Source: Rabaey

2

PLH PHL P

t t t + =

PHL n n

DD

C t W k L

V

≈ ⎞ ⎛ ⎜ ⎟ ⎝ ⎠

Approach 1 Approach 1

EEL7312 – INE5442 Digital Integrated Circuits 15

Dynamic operation - 7

Propagation delay - 4

Source: Rabaey

EEL7312 – INE5442 Digital Integrated Circuits 16

Dynamic operation - 8

( )

1

DS

D

• n

n DD Tn n DS V

dI W R k V V dV L

− =

⎞ ⎛ = = − ⎜ ⎟ ⎝ ⎠

Propagation delay - 5

Modeling capacitor discharge as in an RC circuit!

Source: Rabaey

PHL n n

DD

C t W k L

V

≈ ⎞ ⎛ ⎜ ⎟ ⎝ ⎠

Approach 2 Approach 2

VDD Vout Vin = VDD Ron CL

tpHL = f(Ron.CL) = 0.69 RonCL

t

Vout VDD RonCL

1 0.5 ln(0.5) 0.36

What’s Ron? V

DS(V)

ID(A)

VGS= VDD

VDD VDD/2

Approach by Approach by Uyemura Uyemura

( )

1 2

• n

mid

R R R ≡ +

1

• R−

Approach by Approach by Rabaey Rabaey

1 mid

R−

EEL7312 – INE5442 Digital Integrated Circuits 17

Dynamic operation - 9

( )

1 , ( ) ( ) ( ) ( )

( )

DS

D

• n n p

n p DD Tn p n p DS V

dI W R k V V dV L

− =

+

⎞ ⎛ = = − ⎜ ⎟ ⎝ ⎠

Propagation delay - 6

Source: Uyemura

VDD Vout Vin = VDD Ron CL

tpHL = 0.69 Ron,nCL tpLH = 0.69 Ron,pCL

Approach by Approach by Uyemura Uyemura

( )

( )

0.69 1 1 2 2

PHL PLH L P n DD Tn p DD Tp n p

t t C t W W k V V k V V L L

+

⎡ ⎤ ⎢ ⎥ + ⋅ ⎢ ⎥ = = + ⎞ ⎞ ⎛ ⎛ ⎢ ⎥ − ⎜ ⎟ ⎜ ⎟ ⎢ ⎥ ⎝ ⎝ ⎠ ⎠ ⎣ ⎦

0.69 1 1 [ ] 2

L P DD n p n p

C t W W V k k L L ⋅ ≈ + ⎞ ⎞ ⎛ ⎛ ⎜ ⎟ ⎜ ⎟ ⎝ ⎝ ⎠ ⎠

EEL7312 – INE5442 Digital Integrated Circuits 18

Experimental setup

Dynamic operation - 10

S G B +

• VPULSE

D

2 3 1 1

+

VDD = 5.0 V

• S

G B CL

EEL7312 – INE5442 Digital Integrated Circuits 19

Dynamic operation - 11

Inverter Propagation Delay * this is the Propagationdelay.cir file * PMOS transistor description MP 3 2 1 1 modelp W=2u L=1u .model modelp pmos (level=1 VT0=-0.65 TOX=7.5n KP=60u lambda=0.0) * NMOS transistor description MN 3 2 0 0 modeln W=2u L=1u .model modeln nmos (level=1 VT0=0.5 TOX=7.5n KP=150u lambda=0.0) * dc source vDD 1 0 dc 5.0 *load capacitance CL 3 0 0.01p *signal source v0 2 0 dc 0 pulse 0 5 0 1ps 1ps 200ps 400ps .end

EEL7312 – INE5442 Digital Integrated Circuits 20

Dynamic operation - 12

SpiceOpus (c) 6 -> source Propagationdelay1.cir SpiceOpus (c) 7 -> tran 1ps 500ps SpiceOpus (c) 8 -> setplot new New plot Current tran2 Inverter Propagation Delay (Transient Analysis) tran1 Inverter Propagation Delay (Transient Analysis) const Constant values (constants) SpiceOpus (c) 9 -> setplot tran2 SpiceOpus (c) 10 -> plot v(2) v(3) xlabel t[s] ylabel 'Input, Output [V]'

EEL7312 – INE5442 Digital Integrated Circuits 21

Dynamic operation - 12

Why? tPHL≈2.5·tPLH Why?

EEL7312 – INE5442 Digital Integrated Circuits 22

Dynamic operation - 14

Simulate the transient response of the inverter of the previous exercise for fan-outs of one and two inverters

Exercise

EEL7312 – INE5442 Digital Integrated Circuits 23

Dynamic operation - 15

Design for Performance

Keep capacitances small Increase transistor sizes (W)

watch out for self-loading!

Increase VDD (????)

EEL7312 – INE5442 Digital Integrated Circuits 24

Dynamic operation - 16

Design for Performance

Increase VDD (????)

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5

VDD(V) tp(normalized)

* Velocity saturated devices

Source: Rabaey

EEL7312 – INE5442 Digital Integrated Circuits 25

Dynamic operation - 17

Increase transistor sizes (W)

watch out for self-loading

Design for Performance

tPLH tPHL tPLH0 tPHL0 Propagation delays vs. load capacitance

2 4 6 8 10 12 14 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 x 10

• 11

S tp(sec)

(for fixed load)

Self-loading effect: Intrinsic capacitances dominate

Source: Uyemura Source: Rabaey

min min

W L

min min

SW L

EEL7312 – INE5442 Digital Integrated Circuits 26

Dynamic operation - 18

Design for Performance

Source: Rabaey

Propagation delays vs. PMOS-to-NMOS transistor ratio β=Wp/Wn

1 1.5 2 2.5 3 3.5 4 4.5 5 3 3.5 4 4.5 5 x 10

• 11

β

tp(sec)

tpLH tpHL tp

EEL7312 – INE5442 Digital Integrated Circuits 27

Dynamic operation - 19

Source: Rabaey

tpHL(nsec) 0.35 0.3 0.25 0.2 0.15 trise (nsec) 1 0.8 0.6 0.4 0.2

Impact of Rise Time on Delay Impact of Rise Time on Delay