Logic Characteristics of 40 nm Logic Characteristics of 40 nm Logic - - PowerPoint PPT Presentation

Logic Characteristics of 40 nm Logic Characteristics of 40 nm Logic Characteristics of 40 nm Logic Characteristics of 40 nm thin thin-

• channel

channel InAs InAs HEMTs HEMTs

Tae-Woo Kim, Dae-Hyun Kim* and Jesús A. del Alamo

Microsystems Technology Laboratories MIT *Presently with Teledyne Scientific Sponsors: Intel & FCRP-MSD Fabrication: MTL, NSL, SEBL at MIT IPRM

June 4th, 2009

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Scaling issues in III Scaling issues in III-

• V HEMT

V HEMT

• Motivation

 III-V HEMT: Model system for future III-V logic FETs

 Key dimensions:

• Gate Length (Lg)

Barrier Thickness (t )

Source Drain Gate Source Drain Gate

• Barrier Thickness (tins)
• Side-recess Length (Lside)
• Channel Thickness (tch)

Drain

Source Drain

t

Cap Barrier

Lside Lg

Drain

Source Drain

t

Cap Barrier

Lside Lg

 Scaling trajectory:

• Lg ↓  tins ↓, tch ↓, Lside ↓

tins

Barrier Channel Buffer

tch tins

Barrier Channel Buffer

tch

g ↓ ins ↓,

ch ↓, side ↓

 Goal : Explore trade-offs involved in channel thickness

< Schematic of III-V HEMT >

2

p scaling

Thin channel Thin channel InAs InAs HEMT HEMT

S D

O id

Lg ~ 40 nm

InGaAs/InAlAs

L

g

6 nm InP 11 I Al A Oxide

Lside

tins = 5 nm tch = 5 nm

g

11 nm In0.52Al0.48As

tins tch

In0.7Ga0.3As: 1 nm InAs: 2 nm In0.7Ga0.3As: 2 nm

tch = 5 nm

Buffer : In0.52Al0.48As

T i l t t n,Hall = 9,950 cm2/V-sec

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Triple-step gate recess process

• Gate metal stack: Ti/Pt/Au
• Lside = 80 nm, tins = 5 nm

Reference : InAs HEMT with tch = 10 nm n,Hall = 13,500 cm2/V-sec <D.-H. KIM IEDM 08>

Output & g Output & gm Char.: Char.: L Lg = 40 nm = 40 nm

1.0 tch = 5 nm InAs HEMT tch = 10 nm InAs HEMT VGS = 0.5 V 2.0 tch = 5 nm InAs HEMT tch = 10 nm InAs HEMT 0.6 0.8 VGS = 0.3 V

m ]

Lg = 40 nm 1.2 1.6 S/m] Lg = 40 nm 0.2 0.4 VGS = 0.1 V ID [ mA/ 0.4 0.8 gm [mS 0.0 0.2 0.4 0.6 0.8 0.0 VGS = 0 V VDS [V]

• 0.6
• 0.4
• 0.2

0.0 0.2 0.4 0.6 0.0 VGS [V] VDS = 0.5 V

• Good ID saturation, pinch-off behavior

1 65 S/ @ V 0 5 V

4

• gm = 1.65 mS/m @ VDS=0.5 V

Subthreshold Subthreshold Char.: Char.: L Lg = 40 nm = 40 nm

t h = 5 nm InAs HEMT 1E-4 1E-3 tch 5 s tch = 10 nm InAs HEMT

VDS = 0.05 V VDS = 0.5 V

1E-6 1E-5 /m ] 1E-7 1E-6 ID [ A/

Thin‐channel HEMTs

• Sharper SS
• Lower DIBL

L I /I

1E-9 1E-8 Lg = 40 nm

• Larger ION/IOFF
• 0.6
• 0.4
• 0.2

0.0 0.2 0.4 0.6 VGS [V]

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For tch = 5 nm device at VDS = 0.5 V, SS = 72 mV/dec, DIBL = 72 mV/V and ION/IOFF = 2.5 x 104

Subthreshold Subthreshold Char.

• Char. vs

vs L Lg

10

• 3

LG = 40 nm LG = 50 nm L = 70 nm

10

• 5

10

• 4

LG = 70 nm LG = 80 nm LG = 100 nm LG = 150 nm L = 200 nm

10

• 7

10

• 6

ID [A/m]

LG = 200 nm

Lg  Lg 

10

• 9

10

• 8

VDS = 0.5 V

g

• 0.6
• 0.4
• 0.2

0.0 0.2 0.4 10

9

VGS [V]

6

• Harmonious scaling  Very small VT roll off with Lg (34 mV)

SS & DIBL vs. SS & DIBL vs. L Lg

90 160 80

InAs HEMTs: In0.7Ga0.3As HEMT: tch = 13 nm

ng [mV/dec] 120

V/V]

In0.7Ga0.3As HEMTs: tch = 13 nm

70

InAs HEMTs: tch = 5 nm tch = 10 nm

btreshold swi 80

InAs HEMTs: tch = 10 nm

DIBL [mV

40 80 120 160 200 60 Su Lg [nm] 40 80 120 160 200 40

InAs HEMTs: tch = 5 nm

Lg [nm]

Lside = 80 nm, tins = 5 nm

 Excellent electrostatic integrity and scalability with thin channel

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<D.-H. KIM IPRM 09>

Key trade Key trade-

• off: Source resistance
• ff: Source resistance

< Gate current injection technique>

0.34

tch = 13 nm In0.7Ga0.3As HEMTs

0.30 0.32

Rsheet = 320 Ohm/sq tch = 10 nm InAs HEMTs tch = 5 nm InAs HEMTs

mm] 0.26 0.28

240

280

R

* s [Ohm.m

Rs = 0.255 Ohm mm

40 80 120 160 200 0.22 0.24

Rs = 0.25 Ohm mm Rs = 0.24 Ohm mm

Thin-channel InAs HEMTs:

Lg [nm]

8

• Higher Rsh  higher Rs

<D.-H. KIM IPRM 09>

Scalability of Scalability of g gmi

mi

<gmi from S-parameters>

4 4

In0.7Ga0.3As HEMT: tch = 13 nm InAs HEMT: t = 10 nm

3 3

InAs HEMT: tch 10 nm InAs HEMT: tch = 5 nm

m] 3 3 gmi [mS/m 40 80 120 160 200 2 2 VDS = 0.5 V

Thin-channel InAs HEMTs:

• Lower values of gmi due to lower n

Lg [nm]

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Lower values of gmi due to lower n

• But velocity less affected  better gmi scalability down to 40 nm

fT & & fmax

max char. :

• char. : L

Lg = 40 nm = 40 nm

40

tch = 5 nm devices tch = 10 nm devices f 445 GH 520 GH

1.0

H21

fT 445 GHz 520 GHz fmax 395 GHz 337 GHz

B]

VDS = 0.6 V V = 0 2 V U

20 K H21 & UG [d

VGS 0.2 V Lg = 40 nm

0.5

UG

H

K

1 10 100 1k Frequency [GHz] 0.0

10

For thin-channel InAs HEMT: Low fT but high fmax

Why high Why high f fmax

max ?

?  Evaluation of g Evaluation of go

1.0

m]

Lg = 40 nm 0.6 0.8

ce [mS/mm

InAs HEMT tch = 10 nm

VDS = 0.5 V

g 0.4

InAs HEMT

tch = 5 nm

• nductanc

0 0 0.2 InGaAs HEMT tch = 13 nm

Output co

• Lower DIBL lower Impact ionization:

0.2 0.3 0.4 0.5 0.6 0.7 0.0 ID [mA/mm]

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• Lower DIBL, lower Impact ionization:

 improved output conductance with thin channel

Unified FOM for Logic Unified FOM for Logic

ION at given IOFF and VDD

0.5

ION at given IOFF and VDD

VDD = 0.5 V IOFF = 100 nA/m InAs HEMTs: tch = 5 nm

m] 0.4

InAs HEMTs: tch = 10 nm In0 7Ga0 3As HEMTs:

ION [mA/m 0 3

0.7 0.3 tch = 13 nm

I

32 nm CMOS

10 100 0.3 Lg [nm]

For thin channel InAs HEMT:

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For thin-channel InAs HEMT:  Better scalability in sub – 100nm regime

Conclusion Conclusion

• Thin-channel (tch = 5 nm) InAs HEMTs

– At Lg = 40 nm, thin-channel HEMTs are excellent

g

• DIBL = 72 mV/V, S = 72 mV/dec and ION/IOFF > 104

– Main advantage: improved electrostatics and scalability T d ff 9 950

2/V

R 0 255 Ω – Trade-offs: n = 9,950 cm2/V-sec, Rs = 0.255 Ω·mm

• Future work:
• Future work:

– Increase gate foot stem height ~ 200 nm to improve fT – Extract injection velocity and gate capacitance. Extract injection velocity and gate capacitance. – Optimize barrier to lower Rs and RC.

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