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Spiking row-by-row FPGA Multi-kernel and Multi-layer Convolution - - PowerPoint PPT Presentation
Spiking row-by-row FPGA Multi-kernel and Multi-layer Convolution - - PowerPoint PPT Presentation
Spiking row-by-row FPGA Multi-kernel and Multi-layer Convolution Processor. Ricardo Tapiador Morales Robotic & Tech of Computers Lab, University of Seville ricardo@atc.us.es Convolutional neural networks ricardo@atc.us.es 2
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Neuromorphic Engineering
- Neuromorphic engineering mimics the behavior of the human
brain, where information is encoded in spikes (also called events) that are processed in parallel by massive layers of neurons interconnected via synapses.
Dynamic Vision Sensors
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Dynamic Vision Sensors
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Y: convolution result. K: nxm kernel matrix X: input image
Y X K
- X(i,j) data can be coded in frequency of
events.
- Each event implies to accumulate K into
the Y neighborhood around Y(i,j).
- Y output is based on LIF neuron.
- X, K, Y allows signed values.
- Each (i,j) event implies:
Convolution with Spikes
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Convolution processor architecture: Memory
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Convolution processor architecture: Multi-kernel and Multi-layer mechanisms
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Convolution processor architecture
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Test Scenario
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Results:
Area Performance
- Latency : 1.44-9.98 µs
- Input Throughput : 0.10-0.69 Meps
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Future Works
- Implement a Spiking Convolutional Neural Network
- Add mechanisms to auto-configure the different
parameters
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